Table 2. Design Parameters

10.2.2.1 Step by Step Design Procedure

To begin the design process a few parameters must be decided upon. The designer needs to know the following:

• Normal input operation voltage
• Maximum output capacitance
• Maximum current Limit
• Load during start-up
• Maximum ambient temperature of operation

This design procedure below seeks to control the junction temperature of device under both static and transient conditions by proper selection of output ramp-up time and associated support components. The designer can adjust this procedure to fit the application and design criteria.

10.2.2.2 Programming the Current-Limit Threshold: R_(ILIM) Selection

R_(ILIM) sets the current limit. Using Equation 4.

Equation 10.

Choose the closest standard value: 17.8k, 1% standard value resistor.

10.2.2.3 Undervoltage Lockout and Overvoltage Set Point

The undervoltage lockout (UVLO) and overvoltage trip point are adjusted using the external voltage divider network of R₁, R₂ and R₃ as connected between IN, EN, OVP and GND pins of the TPS25942, TPS25944 devices. The values required for setting the undervoltage and overvoltage are calculated solving Equation 11 and Equation 12.

Equation 11.

where

• V_(OVPR) = OVP Threshold for rising voltage

Equation 12.

where

• V_(ENR) = Enable threshold for rising voltage

For minimizing the input current drawn from the power supply {I_(R123) = V_(IN)/(R₁ + R₂ + R₃)}, it is recommended to use higher values of resistance for R₁, R₂ and R₃.

However, leakage currents due to external active components connected to the resistor string can add error to these calculations. So, the resistor string current, I_(R123) must be chosen to be 20x greater than the leakage current expected.

From the device electrical specifications, V_(OVPR) = 0.99 V and V_(ENR) = 0.99 V. For design requirements, V_(OV) is 16.5 V and V_(UV) is 10.8 V. To solve the equation, first choose the value of R₃ = 31.2 kΩ and use Equation 11 to solve for (R₁ + R₂) = 488.8 kΩ. Use Equation 12 and value of (R₁ + R₂) to solve for R₂ = 16.47 kΩ and finally R₁= 472.33 kΩ.

Using the closest standard 1% resistor values gives R₁ = 475 kΩ, R₂ = 16.7 kΩ, and R₃ = 31.2 kΩ.

The power fail threshold V_(PFAIL) is detected on the falling edge of the power supply. The falling voltage threshold is 7% lower than the rising voltage threshold, so for a set V_(UV) the power fail voltage V_(PFAIL) is given by Equation 13.

10.2.2.4 Programming Current Monitoring Resistor—R_IMON

Voltage at IMON pin V_(IMON) represents the voltage proportional to load current. This can be connected to an ADC of the downstream system for health monitoring of the system. The R_(IMON) need to be configured based on the maximum input voltage range of the ADC used. R_(IMON) is set using Equation 14.

Equation 14.

For I_(LIM) = 5 A, and considering the operating range of ADC from 0 V to 5 V, V_(IMONmax) is 5 V and R_(IMON) is determined by Equation 15:

Equation 15.

Selecting R_(IMON) value less than determined by Equation 15 ensures that ADC limits are not exceeded for maximum value of load current.

If the IMON pin voltage is not being digitized with an ADC, R_(IMON) can be selected to produce a 1V/1A voltage at the IMON pin, using Equation 14.

Choose closest 1 % standard value: 19.1 kΩ.

If current monitoring up to I_(FASTRIP) is desired, R_(IMON) can be reduced by a factor of 1.6, as in Equation 6.

10.2.2.5 Setting Output Voltage Ramp Time (t_dVdT)

For a successful design, the junction temperature of device must be kept below the absolute-maximum rating during both dynamic (start-up) and steady state conditions. Dynamic power stresses often are an order of magnitude greater than the static stresses, so it is important to determine the right start-up time and in-rush current limit required with system capacitance to avoid thermal shutdown during start-up with and without load.

The ramp-up capacitor C_(dVdT) needed is calculated considering the two possible cases:

10.2.2.5.1 Case1: Start-Up Without Load: Only Output Capacitance C_(OUT) Draws Current During Start-Up

During start-up, as the output capacitor charges, the voltage difference across the internal FET decreases, and the power dissipated decreases as well. Typical ramp-up of output voltage V_(OUT) with inrush current limit of 1.2 A and power dissipated in the device during start-up is shown in Figure 56. The average power dissipated in the device during start-up is equal to area of triangular plot (red curve in Figure 57) averaged over t_dVdT.

V(IN) = 12 V

C(dVdT) = 1 nF

C(OUT) = 100 µF

Figure 56. Typical Start-Up Without Load

V(IN) = 12 V

C(dVdT) = 1 nF

C(OUT) = 100 µF

Figure 57. P_D(INRUSH) Due to Inrush Current

For the TPS25944, TPS25944 device, the inrush current is determined as shown in Equation 16.

Equation 16.

Power dissipation during start-up is given by Equation 17.

Equation 17.

Equation 17 assumes that load does not draw any current until the output voltage has reached its final value.

10.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance C_(OUT) and Load Draws Current During Start-Up

When load draws current during the turn-on sequence, there is additional power dissipated. Considering a resistive load R_L(SU) during start-up, load current ramps up proportionally with increase in output voltage during t_dVdT time. Typical ramp-up of output voltage, load current and power dissipated in the device is shown in Figure 58 and power dissipation with respect to time is plotted in Figure 59. The additional power dissipation during start-up phase is calculated as follows shown in Equation 18 and Equation 19.

Equation 18.

Equation 19.

Where R_L(SU) is the load resistance present during start-up. Average energy loss in internal FET during charging time due to resistive load is given by Equation 20.

Equation 20.

V(IN) = 12 V

C(dVdT) = 1 nF, C(OUT) = 100 µF

RL(SU) = 4.8 Ω

Figure 58. Typical Start-Up With Load

V(IN) = 12 V

C(dVdT) = 1 nF, C(OUT) = 100 µF

RL(SU) = 4.8 Ω

Figure 59. P_D(LOAD) in Load During Start-Up

Solving Equation 20 the average power loss in the device due to load is given by Equation 21.

Equation 21.

Total power dissipated in the device during start-up is given by Equation 22.

Equation 22.

Total current during start-up is given by Equation 23.

Equation 23.

If I_(STARTUP) > I_(LIM), the device limits the current to I_(LIM) and the current limited charging time is determined by Equation 24.

Equation 24.

The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 60.

Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm² (Top) and 20 cm² (Bottom)

Figure 60. Thermal Shutdown Limit Plot

For the design example under discussion,

Select ramp-up capacitor C_(dVdT) = 1nF, using Equation 2, we get Equation 25.

Equation 25.

The inrush current drawn by the load capacitance (C_(OUT)) during ramp-up is calculated using Equation 3 and Equation 26.

Equation 26.

The inrush Power dissipation is calculated, using Equation 17 and Equation 27.

Equation 27.

For 7.2 W of power loss, the thermal shut down time of the device must not be less than the ramp-up time t_dVdT to avoid the false trip at maximum operating temperature. From thermal shutdown limit graph Figure 60 at T_A = 85°C, for 7.2 W of power the shutdown time is approximately 60 ms. So it is safe to use 1 ms as start-up time without any load on output.

Considering the start-up with load 4.8 Ω, the additional power dissipation, when load is present during start-up is calculated, using Equation 21 and Equation 28.

Equation 28.

The total device power dissipation during start up is given by Equation 29.

Equation 29.

From thermal shutdown limit graph at T_A = 85°C, the thermal shutdown time for 12.2 W is close to 7.5 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 1 nF capacitor with start-up load of 4.8 Ω.

If there is a need to decrease the power loss during start-up, it can be done with increase of C_(dVdT) capacitor.

To illustrate, choose C_(dVdT) = 1.5 nF as an option and recalculate as shown in Equation 30 to Equation 34.

Equation 30.

Equation 31.

Equation 32.

Equation 33.

Equation 34.

From thermal shutdown limit graph at T_A = 85°C, the shutdown time for 10 W power dissipation is approximately 17 ms, which increases the margins further for shutdown time and ensures successful operation during start-up and steady state conditions.

The spreadsheet tool available on the web can be used for iterative calculations.

10.2.2.6 Programing the Power Good Set Point

As shown in Figure 55, R₄ and R₅ sets the required limit for PGOOD signal as needed for the downstream converters. Considering a power good threshold of 11 V for this design, the values of R₄ and R₅ are calculated using Equation 35.

Equation 35.

It is recommended to have high values for these resistors to limit the current drawn from the output node. Choosing a value of R₄ = 475 kΩ, R₅ = 47 kΩ provides V_(PGTH) = 11 V.

10.2.2.7 Support Component Selections—R₆, R₇ and C_IN

Reference to application schematics, R₆ and R₇ are required only if PGOOD and FLT are used; these resistors serve as pull-ups for the open-drain output drivers. The current sunk by each of these pins must not exceed 10 mA (see the Absolute Maximum Ratings table). C_IN is a bypass capacitor to help control transient voltages, unit emissions, and local supply noise. Where acceptable, a value in the range of 0.001 μF to 0.1 μF is recommended for C_IN.

10.3.1.1 N+1 Power Supply Operation

The devices can be used to combine multiple power supplies to a common bus in an N+1 configuration. The N+1 power supply configuration as shown in Figure 78, is used where multiple power supplies are paralleled for either higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra identical unit in parallel permits the load to continue operation in the event that any one of the N supplies fails. The devices emulate the function of the ORing diode and provides with all protections as needed to isolate the rail during hot-plug, overvoltage, undervoltage, overcurrent and short-circuit conditions.

Figure 78. N+1 Configuration Implementation

10.3.1.2 Priority Power MUX Operation

Applications having two energy sources such as PCIe cards, Tablets and Portable battery powered equipment require preference of one source to another. For example, mains power (wall-adapter) has the priority over the internal back-up power or auxiliary power. These applications demand for switch over from mains power to back-up power only when main input voltage falls below a user defined threshold. The devices provide a simple solution for priority power multiplexing needs.

Figure 79 shows a typical priority power multiplexing implementation using devices. When primary power IN1 is present, the device in IN1 path powers the OUT bus irrespective of whether auxiliary power IN2 is greater than or less than IN1. Once the voltage on the IN1 rail falls below the user-defined threshold, the device IN1 issues a signal to switch over to auxiliary power IN2. The transition happens seamlessly in less than 125 µs, with minimal voltage droop on the bus. The voltage droop during transition is a function of load current and bus capacitance (see Equation 36).

Equation 36.

where

• V_(droop) in Volts, I_(Load) is load current in Ampere, C_(BUS) is bus capacitance in µF

When the main voltage supply (IN1) is not present or during brown-out conditions, the device in auxiliary supply rail (IN2) provides power to the output. When IN1 recovers, the device connected to IN1 is turned on at defined slew rate and the device in IN2 path is turned off, allowing a seamless transition from auxiliary to the main voltage supply with minimal droop and with no shoot-through current.

Priority power multiplexing can be done either between two similar rails (such as 12 V Primary to 12 V Aux, 3.3 V Primary to 3.3 V Aux) or between dissimilar rails (such as 12 V Primary to 5 V Aux or 3.3 V Aux; or vice versa).

A. C_IN: Optional and only for noise suppression.

B. Master controls the slave using priority signal for switch over to Auxiliary power.

Figure 79. Priority Power Multiplexing Implementation

Figure 80 and Figure 81 show typical switch-over waveforms of Priority Muxing implementation using the TPS25942 or TPS25944 for 11.5 V Primary and 14.5 V Auxiliary Bus.

Figure 82 and Figure 83 show typical switch-over waveforms of Priority Muxing implementation using the TPS25942 or TPS25944 for 12 V Primary and 3.3 V Auxiliary Bus.

V(IN1) = 11.5 V	R(ILIM1) = 24.6 kΩ,	C(OUT) = 150 µF
V(IN2) = 14.5 V	R(ILIM2) = 33.2 kΩ	C(dVdT) = 1.2 nF
RL = 5.6 Ω	R(IMON) = 16.2 kΩ	V(UVLO-High) = 10.8 V

Figure 80. IN1 Power Recovery: Change Over from Auxiliary IN2 to Primary Power IN1

V(IN1) = 12 V	R(ILIM1) = 24.6 kΩ	C(OUT) = 150 µF
V(IN2) = 3.3 V	R(ILIM2) = 33.2 kΩ	C(dVdT) = 1.2 nF
RLoad = 5.6 Ω	R(IMON) = 16.2 kΩ	V(UVLO-High) = 10.8 V

Figure 82. IN1 Power Recovery: Change Over from Auxiliary IN2 to Main Power IN1

V(IN1) = 11.5 V	R(ILIM1) = 24.6 kΩ	C(OUT) = 150 µF
V(IN2) = 14.5 V	R(ILIM2) = 33.2 kΩ	C(dVdT) = 1.2 nF
RL = 5.6 Ω	R(IMON) = 16.2 kΩ	V(UVLO-Low) = 10.2 V

Figure 81. IN1 Brownout Condition: Change Over from Main IN1 to Auxiliary Power IN2

V(IN1) = 12 V	R(ILIM1) = 24.6 kΩ	C(OUT) = 150 µF
V(IN2) = 3.3 V	R(ILIM2) = 33.2 kΩ	C(dVdT) = 1.2 nF
RL = 5.6 Ω	R(IMON) = 16.2 kΩ	V(UVLO-Low) = 10.2 V

Figure 83. IN1 Brownout Condition: Change Over from Main IN1 to Auxiliary Power IN2

10.3.1.3 Priority MUXing With Almost Equal Rails (V_IN1 ~ V_IN2)

Most of the redundant power supply systems used in servers, storage and telecom, multiplex tightly regulated power rails to provide uninterrupted power to the load. In these systems, the primary and auxiliary rails are close to each other, typically within one diode drop when both rails are active.

For priority multiplexing in these systems, the TPS25942 or TPS25944 device in auxiliary rail path can be operated in Diode Mode for a fast switch-over (1 µs typical). The fast switch-over reduces the required hold-up capacitor on the output rail for a given droop specification.

The circuit implementation of this configuration is shown in Figure 84. During power-fail (brown-out) conditions of primary rail IN1, it changes IN2 from ‘Diode-Mode’ to normal operation using PGOOD. Similarly during power recovery of primary rail IN1, the auxiliary rail IN2 is driven into ‘Diode-Mode’.

Figure 84. Priority Power Multiplexing Configuration for Almost Equal Rails

The fast switch-over performance is shown in Figure 85.

C(OUT) = 150 µF

RL = 4 Ω

Figure 85. Brownout Condition: Diode Mode for Multiplexing

10.3.1.4 Reverse Polarity Protection

In applications demanding reverse polarity or reverse battery protection, the TPS25942 and TPS25944 can be used as an eFuse or ideal diode. A typical reverse polarity protection circuitry is shown in Figure 86. The signal diode in the GND terminal path ensures that device is not functional during reverse polarity conditions and internal FET blocks the reverse path.

Figure 86. Reverse Polarity Protection Implementation