Table 1. DFP-to-UFP Connections

Table 2. TPS25810A-Q1 Response

Table 3. USB Type-C Current Advertisement

8.3.3.1 Device Power Pins (IN1, IN2, AUX, OUT, and GND)

The device has multiple input power pins: IN1, IN2 and AUX. IN1 is connected to OUT by the internal power FET and serves as the supply for the Type-C charging current. IN2 is the supply for V_CONN and ties directly between the V_CONN power switch on its input and CC1 or CC2 on its output. AUX, the auxiliary input supply, provides power to the device. See the Functional Block Diagram.

In the simplest implementation where multiple supplies are not available, IN1, IN2, and AUX can be tied together. However, in mobile systems (battery powered) where system power savings is paramount, IN1 and IN2 can be powered by the high-power dc-dc supply (>3-A capability), and AUX can be connected to the low-power supply that typically powers the system microcontroller when the system is in the hibernate or sleep power state. Unlike IN1 and IN2, AUX can operate directly from a 3.3-V supply commonly used to power the microcontroller when the system is put in low-power mode. Ceramic bypass capacitors close to the device from the INx and AUX pins to GND are recommended to alleviate bus transients.

The recommended operating voltage range for IN1 and IN2 is 4.5 V to 5.5 V, whereas AUX can be operated from 2.9 V to 5.5 V. However IN1, the high-power supply, can operate up to 6.5 V. This higher input voltage affords a larger IR loss budget in systems where a long cable harness is used, and results in high IR losses with 3-A charging current. Increasing IN1 beyond 5.5 V enables longer cable and board trace lengths between the device and the Type-C receptacle while meeting the USB specification for V_BUS ≥ 4.75 V at the connector.

Figure 14 illustrates the point. In this example IN1 is at 5 V, which restricts the IR loss budget from the dc-dc converter to the connector to 250 mV.

Figure 14. Total IR Loss Budget

8.3.3.2 FAULT Response

The FAULT pin is an open-drain output asserted low when the device OUT current exceeds its programmed value and the overtemperature threshold (T_{TH_OTSD1}) is crossed. See the Electrical Characteristics for overcurrent and overtemperature values. The FAULT signal remains asserted until the fault condition is removed and the device resumes normal operation. An internal deglitch circuit eliminates false overcurrent-fault reporting.

Connect FAULT with a pullup resistor to AUX. FAULT can be left open or tied to GND when not used.

8.3.3.3 Thermal Shutdown

The device has two internal overtemperature shutdown thresholds, T_{TH_OTSD1} and T_{TH_OTSD2}, to protect the internal FET from damage and assist with overall safety of the system. T_{TH_OTSD2} is greater than T_{TH_OTSD1}. FAULT is asserted low to signal a fault condition when the device temperature exceeds T_{TH_OTSD1} and the current-limit switch is disabled. However, when T_{TH_OTSD2} is exceeded, all open-drain outputs are left open and the device is disabled such that minimum power is dissipated. The device attempts to power up when the die temperature decreases by 20°C.

8.3.3.4 REF

A 100-kΩ (1% or better recommended) resistor is connected from this pin to REF_RTN. The REF pin sets the reference current required to bias the internal circuitry of the device. The overload current-limit tolerance and CC currents depend upon the accuracy of this resistor. Using a ±1% or better low-temperature-coefficient resistor yields the best current-limit accuracy and overall device performance.

8.3.3.5 Audio Accessory Detection

The USB Type-C specification defines an audio-adapter decode state which allows implementation of an analog USB Type-C to 3.5-mm headset adapter. An audio accessory device is detected when both CC1 and CC2 pins detect V_Ra voltage (when pulled to ground by an Ra resistor). The open-drain AUDIO pin is asserted low to indicate the detection of such a device.

Platforms supporting the audio accessory function can be triggered by the AUDIO pin to enable accessory mode circuits to support the audio function. When the Ra pulldown is removed from the CC2 pin, AUDIO is deasserted or pulled high. The TPS25810A-Q1 device monitors the CC2 pin for audio device detach. When this function is not needed (for example in a data-less port), AUDIO can be tied to GND or left open.

8.3.3.6 Debug Accessory Detection

The Type-C spec supports an optional debug-accessory mode, used for debug only and not to be used for communicating with commercial products. When the TPS25810A-Q1 device detects V_Rd voltage on both CC1 and CC2 pins (when pulled to ground by an Rd resistor), it asserts DEBUG low. With DEBUG asserted, the system can enter debug mode for factory testing or a similar functional mode. DEBUG deasserts or pulls high when Rd is removed from CC1. The CC1 pin is monitored for debug-accessory detach.

If the debug-accessory mode is not used, tie DEBUG to GND or leave it open.

8.3.3.7 Plug Polarity Detection

Reversible Type-C plug orientation is reported by the POL pin when a UFP is connected. However, when no UFP is attached POL remains deasserted, irrespective of cable plug orientation. Table 6 describes the POL state based on which of the device CC pins detects V_Rd from an attached UFP pulldown.

Figure 15 shows an example implementation which uses the POL terminal to control the SEL terminal on the HD3SS3212 device. The HD3SS3212 device provides switching on the differential channels between Port B and Port C to Port A, depending on cable orientation. For details on the HD3SS3212 device, see HD3SS3212x Two-Channel Differential 2:1/1:2 USB3.1 Mux/Demux.

Figure 15. Example Implementation

8.3.3.8 Device Enable Control

The logic enable pin (EN) controls the power switch and device supply current. The supply current is reduced to less than 1 μA when a logic low is present on EN. The EN pin provides a convenient way to turn on or turn off the device while it is powered. The enable input threshold has built-in hysteresis. When this pin is pulled high, the device is turned on or enabled. When the device is disabled (EN pulled low) the internal FETs tied to IN1 and IN2 are disconnected, all open-drain outputs are left open (Hi-Z), and the monitor block for CC1 and CC2 is turned off. The EN terminal should not be left floating.

8.3.3.9 Cable Compensation (CS)

The TPS25810A-Q1 device monitors the current to a UFP, and if the load current exceeds 1.95 A (typ), the CS pin asserts. This can be useful for implementing a digital droop-compensation scheme by altering the feedback resistor ratio of the IN1 power source.

Figure 16 shows a USB charging design using the TPS25810A-Q1 device. The 5-V (typical) nominal output of the USB power supply, designated 5 V_OUT herein, is often a dc-dc converter in automotive applications. V_{UFP_IN} refers to the voltage across the inside contacts of the USB connector of a UFP device. Official USB specifications should be consulted for the most up-to-date requirements. For illustration purposes, it is assumed the minimum and maximum voltages allowed for V_{UFP_IN} are 4 V and 5.25 V, respectively. In general, when V_{UFP_IN} is 5 V, the UFP draws optimum current and requires the minimum amount of time to recharge its battery.

Figure 16. TPS25810A-Q1 Charging System Schematic

In a practical system, there are voltage drops from the dc-dc output, 5 V_OUT, to V_{UFP_IN} which include the on-resistance of the TPS25810A-Q1 device power switch, USB cabling and connector contact resistances. Under rated UFP load current, these drops can be several hundred millivolts, decreasing V_{UFP_IN} below the optimal 5-V level. In addition, as V_{UFP_IN} decreases below 5 V, most modern UFPs decrease their load current to prevent possible overload conditions and to maintain V_{UFP_IN} above 4 V. Lower-than-optimum load current increases the time required to recharge the UFP battery. For example, in Figure 16, assuming that the loss resistance is 113 mΩ (includes 79 mΩ of USB cable resistance and 34 mΩ of power switch resistance) and 5 V_OUT is 5 V, the input voltage of UFP (V_{UFP_IN}) is about 4.66 V at 3 A. The TPS25810A-Q1 device provides the CS pin to report high-charging-current conditions and increase the 5 V_OUT voltage as shown in Figure 17

Figure 17. TPS25810A-Q1 CS Function

Equation 1 through Equation 4 refer to Figure 16

The power supply output voltage is calculated in Equation 1.

Equation 1.

5 V_OUT and V_FB are known. If R₃ is given and R₁ is fixed, R₂ can be calculated. The 5 V_OUT voltage change with compensation is shown in Equation 2 and Equation 3.

Equation 2.

Equation 3.

If R₁ is less than R₃, then Equation 3 can be simplified as Equation 4.

Equation 4.

8.3.3.10 Power Wake

The power-wake feature offers the mobile-systems designer a way to save on system power when no UFP is attached to the Type-C port. See Figure 18. To enable power wake, the UFP pins from any combination of two TPS25810A-Q1 devices are tied together (each with its own 100-kΩ pullup) to the enable pin of a 5-V, 6-A dc-dc buck converter. When no UFP is detected on both Type-C ports, the EN pin of the dc-dc converter is pulled high, thereby disabling it. Because the TPS25810A-Q1 device is powered by an always-on 3.3-V LDO, turning off the supply to IN1 and IN2 does not affect its operation in the detach state. Anytime a UFP is detected on either port, the corresponding UFP pin is pulled low, enabling the dc-dc converter to provide charging current to the attached UFP. Turning off the high-power dc-dc converter when ports are unattached saves on system power. This method can save a significant amount of power, because the TPS25810A-Q1 device requires only 0.7 µA (typical) via the AUX pin when no UFP device is connected.

Figure 18. Power-Wake Implementation