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SLIS149 June 2014 TPL0102-EP

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PW|14
- MPDS360A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
V_DD to GND	Supply voltage	–0.3	7	V
V_SS to GND		–7	0.3	V
V_DD to V_SS			7	V
V_H, V_L, V_W	Voltage at resistor pins	V_SS – 0.3	V_DD + 0.3	V
V_I	Digital input voltage	–0.3	V_DD + 0.3	V
I_H, I_L, I_W	Pulse current		±20	mA
I_H, I_L, I_W	Continuous current		±2	mA

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

(3) All voltages are with respect to ground, unless otherwise specified.

7.2 Handling Ratings

		MIN	MAX	UNIT
T_stg	Storage temperature range	–65	150	°C

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_DD, V_SS	Single supply operation (V_SS= 0 V)	2.7	5.5	V
V_DD, V_SS	Dual supply operation	±2.25	±2.75	V
V_H, V_L	Pin voltage	V_SS	V_DD	V
V_IH	Voltage input high (SCL, SDA, A0, A1, A2)	0.7 × V_DD	5.5	V
V_IL	Voltage input low (SCL, SDA, A0, A1, A2)	0	0.3 × V_DD	V
I_W	Wiper current		±2	mA
T_J	Junction temperature	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPL0102-EP	UNIT
		PW
		14 PINS
R_θ_JA	Junction-to-ambient thermal resistance⁽²⁾	112.9	°C/W
R_θ_JC(top)	Junction-to-case (top) thermal resistance⁽³⁾	39.9
R_θ_JB	Junction-to-board thermal resistance⁽⁴⁾	55.9
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	3.5
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	55.2
R_θ_JC(bot)	Junction-to-case (bottom) thermal resistance⁽⁷⁾	N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

7.5 Electrical Characteristics

V_DD = 2.7 to 5.5 V, V_SS = 0 V, V_H= V_DD, V_L= GND, T_J= –40°C to 125°C (unless otherwise noted). Typical values are at
V_DD = 5 V, T_J= 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
R_TOT	End-to-end resistance (Between H and L pins)	TPL0102-100		80	100	120	kΩ
R_H, R_L	Pin resistance				60	200	Ω
R_W	Wiper resistance				25	120	Ω
C_H, C_L⁽¹⁴⁾⁽¹⁵⁾	Pin capacitance				22		pF
C_W⁽¹⁴⁾⁽¹⁵⁾	Wiper capacitance				16		pF
I_LKG	Pin leakage current	V_H = V_SS to V_DD, V_L = Floating or V_L = V_SS to V_DD, V_H = Floating			0.1	1	µA
TC_R	Resistance temperature coefficient	Input Code = 0x80h			92		ppm/°C
R_TOT,MATCH	Channel-to-channel resistance match				0.1		%
VOLTAGE DIVIDER MODE
INL⁽¹⁾⁽³⁾	Integral non-linearity			–0.5		0.5	LSB
DNL⁽¹⁾⁽⁴⁾	Differential non-linearity			–0.25		0.25	LSB
ZS_ERROR⁽²⁾⁽⁵⁾	Zero-scale error			0	0.1	2	LSB
FS_ERROR⁽²⁾⁽⁶⁾	Full-scale error			–2	–0.1	0	LSB
V_MATCH⁽²⁾⁽⁷⁾	Channel-to-channel matching	Wiper at the same tap position, same voltage at all H and same voltage at all L pins		–2		2	LSB
TC_V	Ratiometric temperature coefficient	Wiper set at mid-scale			4		ppm/°C
BW	Bandwidth	TPL0102-100	Wiper set at midscale C_LOAD = 10 pF		229		kHz
T_SW	Wiper setting time	TPL0102-100			3.6		µS
THD	Total harmonic distortion	V_H = 1 V_RMS at 1 kHz, V_L = (V_DD – V_SS)/2, Measurement at W	TPL0102-100		0.03		%
X_TALK	Crosstalk	ƒ_H = 1 kHz, V_L = GND, Measurement at W			–82		dB
RHEOSTAT MODE (Measurements between W and L with H not connected, or between W and H with L not connected)
RINL⁽⁸⁾⁽¹⁰⁾	Integral non-linearity			–1		1	LSB
RDNL⁽⁸⁾⁽¹¹⁾	Differential non-linearity			–0.5		0.5	LSB
R_OFFSET⁽⁹⁾⁽¹²⁾	Offset			0	0.2	2	LSB
R_MATCH⁽⁹⁾⁽¹³⁾	Channel-to-channel matching			–2		2	LSB
RBW	Bandwidth	Code = 0x00h, L Floating, Input applied to W, Measure at H, C_LOAD = 10 pF	TPL0102-100		54		kHz

(1) LSB = (V_{MEAS[code 255]} – V_{MEAS[code 0]}) / 255

(2) IDEAL_LSB = (V_H – V_L) / 256

(3) INL = ((V_{MEAS[code x]} – V_{MEAS[code 0]}) / LSB) – [code x]

(4) DNL = ((V_{MEAS[code x]} – V_{MEAS[code x-1]}) / LSB) – 1

(5) ZS_ERROR = V_{MEAS[code 0]} / IDEAL_LSB

(6) FS_ERROR = [(V_{MEAS[code 255]} – (V_H – V_L)) / IDEAL_LSB] + 1

(7) V_MATCH = (V_{MEAS_A[code x]} – V_{MEAS_B[code x]}) / IDEAL_LSB

(8) RLSB = (R_{MEAS[code 255]} – R_{MEAS[code 0]}) / 255

(9) IDEAL_RLSB = R_TOT / 256

(10) RINL =( (R_{MEAS[code x]} – R_{MEAS[code 0]}) / RLSB) – [code x]

(11) RDNL =( (R_{MEAS[code x]} – R_{MEAS[code x-1]}) / RLSB ) – 1

(12) R_OFFSET = R_{MEAS[code 0]} / IDEAL_RLSB

(13) R_MATCH = (R_{MEAS_A[code x]} – R_{MEAS_B[code x]}) / IDEAL_RLSB

(14) Pin and wiper capacitance extracted from self admittance of three port network measurement

(15) Digital Potentiometer Macromodel

1. See data sheet for absolute maximum and minimum recommended operating conditions.

2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).

3. Enhanced plastic product disclaimer applies.

Figure 1. TPL0102-EP Electromigration Fail Mode/Wirebond Life Derating Chart

7.6 Operating Characteristics

V_DD = 2.7 to 5.5 V, V_SS = 0 V, V_H= V_DD, V_L = GND, T_J= –40°C to 125°C (unless otherwise noted). Typical values are at
V_DD = 5 V, T_J = 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_DD(STBY)	V_DD standby current	V_DD = 2.75 V, V_SS = –2.75 V, I²C interface in standby mode	–40°C		0.2	1.5	µA
			25°C			1
			125°C			16
I_SS(STBY)	V_SS standby current	V_DD = 2.75 V, V_SS = –2.75 V, I²C interface in standby mode	–40°C	–1.5	–0.2		µA
			25°C	–1
			125°C	–16
I_DD(SHUTDOWN)	V_DD shutdown current	V_DD = 2.75 V, V_SS = –2.75 V, I²C interface in standby mode	–40°C		0.2	1.5	µA
			25°C			1
			125°C			16
I_SS(SHUTDOWN)	V_SS shutdown current	V_DD = 2.75 V, V_SS = –2.75 V, I²C interface in standby mode	–40°C	–1.5	–0.2		µA
			25°C	–1
			125°C	–16
I_DD	V_DD current during non-volatile write	V_DD = 2.75 V, V_SS = –2.75 V				350	µA
I_SS	V_SS current during non-volatile write	V_DD = 2.75 V, V_SS = –2.75 V		-350			µA
I_LKG-DIG	Digital pins leakage current (A0, A1, A2, SDA, and SCL)			–1		1	µA
V_POR	Power-on recall voltage	Minimum V_DD at which memory recall occurs			2		V
EEPROM SPECIFICATION
	EEPROM endurance				1000		Cycles
	EEPROM retention				100000		Hours
t_WC	Non-volatile write cycle time				20		ms
WIPER TIMING CHARACTERISTICS
t_WRT	Wiper response time	SCL falling edge of last bit of wiper data byte to wiper new position			600		ns
t_SHUTDOWNREC	Wiper position recall time from shut-down mode	SCL falling edge of last bit of ACR data byte to wiper stored position and H connection			800		ns
t_D	Power-up delay	V_DD above V_POR, to wiper initial value register recall completed, and I²C interface in standby mode			35	100	µs
C_IN	Pin capacitance	A0, A1, A2, SDA SCL pins			7		pF
I²C INTERFACE SPECIFICATIONS
V_IH	Input high voltage			0.7 × V_DD		5.5	V
V_IL	Input low voltage			0		0.3 × V_DD	V
V_OL	Output low voltage	SDA pin, I_OL = 4 mA				0.4	V
C_IN	Pin capacitance	A0, A1, A2, SDA SCL pins			7		pF

7.7 Timing Requirements

V_DD = 2.7 to 5.5 V, V_SS = 0 V, V_H = V_DD, V_L = GND, T_J = –40°C to 125°C (unless otherwise noted). Typical values are at
V_DD = 5 V, T_J = 25°C (unless otherwise noted).

		STANDARD MODE I²C BUS		FAST MODE I²C BUS		UNIT
		MIN	MAX	MIN	MAX	UNIT
I²C INTERFACE TIMING REQUIREMENTS
ƒ_SCL	I²C clock frequency	0	100	0	400	kHz
t_SCH	I²C clock high time	4		0.6		µs
t_SCL	I²C clock low time	4.7		1.3		µs
t_sp	I²C spike time	0	50	0	50	ns
t_SDS	I²C serial data setup time	250		100		ns
t_SDH	I²C serial data hold time	0		0		ns
t_ICR	I²C input rise time		1000	20 + 0.1C_b⁽¹⁾	300	ns
t_ICF	I²C input fall time		300	20 + 0.1C_b⁽¹⁾	300	ns
t_ICF	I²C output fall time, 10- to 400-pF bus		300	20 + 0.1C_b⁽¹⁾	300	ns
t_BUF	I²C bus free time between stop and start	4.7		1.3		µs
t_STS	I²C start or repeater start conditions setup time	4.7		1.3		µs
t_STH	I²C start or repeater start condition hold time	4		0.6		µs
t_SPS	I²C stop condition setup time	4		0.6		µs
t_VD(DATA)	Valid data time, SCL low to SDA output valid		1		1	µs
t_VD(DATA)	Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low		1		1	µs