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SLVSA55B November 2009 – November 2016 TPD4S1394

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DQL|8
- MPSS015

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

DQL|8
- QFND219A

訂購(gòu)信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage	–0.5	4.6	V
V_IO	IO voltage at D+, D–, V_CLMP	0	4	V
FWPWR_EN	Switch output	–0.5	4.6	V
T_A	Operating free-air temperature	–40	85	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins except 5, 6, 7, and 8	±2500	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	Pins 5, 6, 7, and 8	±15000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	All pins except 5, 6, 7, and 8	±1000
			Pins 5, 6, 7, and 8	±1000
		IEC 61000-4-2 contact discharge	Pins 5, 6, 7, and 8 (interface side)	±6000
		IEC 61000-4-2 air-gap discharge	Pins 5, 6, 7, and 8 (interface side)	±6000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT
V_CC	Supply voltage	3	3.6	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPD4S1394	UNIT
		DQL (X2SON)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	167.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	56.8	°C/W
R_θJB	Junction-to-board thermal resistance	82.3	°C/W
ψ_JT	Junction-to-top characterization parameter	1.5	°C/W
ψ_JB	Junction-to-board characterization parameter	82	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_DX	FWPWR_EN trip voltage (D+ and D– pins)	High-to-low		2.9	3.4	4	V
V_DX	FWPWR_EN trip voltage (D+ and D– pins)	Low-to-high		2.7	3.2	3.8	V
V_CLMP	Value on pin		No connection		2.45		V
V_BR	Breakdown voltage at V_CLAMP		I_I = 1 mA		4.2		V
V_D	Diode forward voltage for lower clamp		I_D = 8 mA lower clamp diode	–0.6	–0.8	–0.95	V
FWPWR_EN	Switch output				V_CC		V
R_DYN	Dynamic resistance (in and out clamp) of D+, D–		I = 1 A		1		Ω
C_IO	I/O capacitance of D+, D–		V_IO = 2.5 V		1.5	2	pF
I_CC	Current consumption		V_CC = 3.3 V, FWPWR_EN = high		130	200	µA

(1) A 0.1-µF decoupling capacitor is required at VCC.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_TRIP	Delay time for FWPWR_EN to go low	Loading on FWPWR_EN = 50 pF	0.5	2	5	µs
t_RESET	Delay time for FWPWR_EN to go high after trip	FWPWR_EN = V_CC	300	450	600	ms

6.7 Typical Characteristics

D+, D– Pins

Figure 1. I/O Capacitance vs I/O Voltage

D+, D– Pins

Figure 2. Insertion Loss (S21)