ZHCSAL0D March 2016 – August 2020 TPD3S716-Q1
PRODUCTION DATA
Figure 9-2 USB2.0 Eye Diagram (Board only, Through Path)
Figure 9-4 50-V, 1-μF X7R Ceramic Shorted to 18-V (Not Recommended)
Figure 9-6 TPD3S716-Q1 and 100-V, 1-μF X7R Shorted to 18 V (Powered Off)
Figure 9-8 TPD3S716-Q1 Maximum VBUS RON vs. Junction Temperature
Figure 9-3 USB2.0 Eye Diagram (System from Typical Application Schematic)
Figure 9-5 100-V, 1-μF X7R Ceramic Shorted to 18 V
Figure 9-7 TPD3S716-Q1 IVBUS Temperature Derating Curve