ZHCSH87B September 2017 – February 2020 TMP461-SP
PRODUCTION DATA.
| FAST MODE | HIGH-SPEED MODE | UNIT | |||||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| f(SCL) | SCL operating frequency | 0.001 | 0.4 | 0.001 | 2.17 | MHz | |
| t(BUF) | Bus free time between stop and start condition | 1300 | 160 | ns | |||
| t(HDSTA) | Hold time after repeated start condition.
After this period, the first clock is generated. |
600 | 160 | ns | |||
| t(SUSTA) | Repeated start condition setup time | 600 | 160 | ns | |||
| t(SUSTO) | Stop condition setup time | 600 | 160 | ns | |||
| t(HDDAT) | Data hold time | 0 | 900 | 0 | 150 | ns | |
| t(SUDAT) | Data setup time | 100 | 40 | ns | |||
| t(LOW) | SCL clock low period | 1300 | 320 | ns | |||
| t(HIGH) | SCL clock high period | 600 | 60 | ns | |||
| tF – SDA | Data fall time | 300 | 130 | ns | |||
| tF, tR – SCL | Clock fall and rise time | 300 | 40 | ns | |||
| tR | Rise time for SCL ≤ 100 kHz | 1000 | ns | ||||
| SUBGROUP | DESCRIPTION | TEMPERATURE (°C) |
|---|---|---|
| 1 | Static tests at | 25 |
| 2 | Static tests at | 125 |
| 3 | Static tests at | –55 |
| 4 | Dynamic tests at | 25 |
| 5 | Dynamic tests at | 125 |
| 6 | Dynamic tests at | –55 |
| 7 | Functional tests at | 25 |
| 8A | Functional tests at | 125 |
| 8B | Functional tests at | –55 |
| 9 | Switching tests at | 25 |
| 10 | Switching tests at | 125 |
| 11 | Switching tests at | –55 |
Figure 1. Two-Wire Timing Diagram