ZHCS490B November 2011 – December 2018 TMP104
PRODUCTION DATA.
- 1特性
- 2應(yīng)用
- 3說明
- 4修訂歷史記錄
- 5Pin Configuration and Functions
- 6Specifications
- 7Detailed Description
- 8器件和文檔支持
- 9機械、封裝和可訂購信息
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- YFF|4
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.2.3 SMAART Wire™ Interface Timing Specifications
Figure 6 shows the key timing and jitter considerations for the SMAART wire interface. Table 1 lists the timing specifications for ensured, reliable operation. During a transaction, the baud rate must remain within ±1% of its initialization byte value; however, the baud rate can change from transaction to transaction. There is an allowed delay between each byte transfer of less than 28 ms, which is the bus inactivity timeout check for the TMP104 SMAART wire interface.
Figure 6. SMAART Wire™ Timing Diagram Table 1. Timing Diagram Definitions
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| Baud | 4.8 k | 114 k | Bits/s | |
| tR | Clock/data rise time | 0.5 | %Baud | |
| tF | Clock/data fall time | 0.5 | %Baud | |
| Jitter | ±1 | %Baud | ||