欧美无人区码卡二卡3卡2022,国产小嫩模无套中出视频

ZHCSOO2B December 2022 – March 2024 THVD2410V , THVD2412V , THVD2450V , THVD2452V

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRC|10
- MPDS117L

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

DRC|10
- QFND013N

訂購(gòu)信息

5.11 Switching Characteristics_50 Mbps

50-Mbps (THVD2450V, THVD2452V with SLR = 0) over recommended operating conditions. All typical values are at 25°C and supply voltage of V_CC = 5 V, V_IO = 3.3 V, unless otherwise noted. ⁽¹⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
Driver
t_r, t_f	Differential output rise/fall time	R_L = 54 Ω, C_L = 50 pF See Figure 6-3	V_CC = 3 to 3.6 V, Typical at 3.3 V	1	5	7	ns
t_r, t_f	Differential output rise/fall time		V_CC = 4.5 to 5.5 V, Typical at 5 V	1	5	6	ns
t_PHL, t_PLH	Propagation delay		V_IO = 3 V to 3.6 V, V_CC = 3 to 3.6 V, Typical at 3.3 V	5	11	19	ns
			V_IO = 1.65 V to 1.95 V, V_CC = 3 to 3.6 V, Typical at 3.3 V	7	12	22	ns
			V_IO = 3 V to 3.6 V, V_CC = 4.5 to 5.5 V, Typical at 5 V	4	8	15	ns
			V_IO = 1.65 V to 1.95 V, V_CC = 4.5 to 5.5 V, Typical at 5 V	6	10	19	ns
t_SK(P)	Pulse skew, \|t_PHL – t_PLH\|		V_CC = 3 to 3.6 V, Typical at 3.3 V		1	3	ns
t_SK(P)	Pulse skew, \|t_PHL – t_PLH\|		V_CC = 4.5 to 5.5 V, Typical at 5 V		1	3	ns
t_PHZ, t_PLZ	Disable time	RE = X	See Figure 6-4 and Figure 6-5		14	30	ns
t_PZH, t_PZL	Enable time	RE = 0 V ; V_IO = 1.65 V to 1.95 V, 2.25 V to 2.75 V			20	35	ns
		RE = 0 V ; V_IO = 3 V to V_CC V			15	32	ns
		RE = V_IO			2.5	4.5	μs
t_SHDN	Time to shutdown	RE = V_IO		50		500	ns
Receiver
t_r, t_f	Output rise/fall time	C_L = 15 pF	See Figure 6-6		1.5	6	ns
t_PHL, t_PLH	Propagation delay	C_L = 15 pF	V_IO = 3 V to 3.6 V, See Figure 6-6	25	33	58	ns
t_PHL, t_PLH	Propagation delay		V_IO = 1.65 V to 1.95 V, See Figure 6-6	25	35	60	ns
t_SK(P)	Pulse skew, \|t_PHL – t_PLH\|	C_L = 15 pF	See Figure 6-6		0.5	5	ns
t_PHZ, t_PLZ	Disable time	DE = X			12	25	ns
t_PZH(1), t_PZL(1)	Enable time	DE = V_IO	V_IO = 1.65 V to 1.95 V, See Figure 6-7		50	82	ns
t_PZH(1), t_PZL(1)	Enable time	DE = V_IO	V_IO = 3 V to 3.6 V, See Figure 6-7		50	75	ns
t_PZH(2), t_PZL(2)	Enable time	DE = 0 V	See Figure 6-8		2.8	5	μs
t_D(OFS)	Delay to enter fail-safe operation	C_L = 15 pF	See Figure 6-9	7	10	18	μs
t_D(FSO)	Delay to exit fail-safe operation	C_L = 15 pF	See Figure 6-9	19	32	50	ns
t_SHDN	Time to shutdown	DE = 0 V	See Figure 6-8	50		500	ns

(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for Full duplex device