ZHCSJZ2F August 2019 – December 2024 THS6222
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- YS|0
- RGT|16
- RHF|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGT|16
訂購(gòu)信息
4 Pin Configuration and Functions
Figure 4-1 RHF Package,
24-Pin VQFN With Exposed Thermal Pad
(Top View)
24-Pin VQFN With Exposed Thermal Pad
(Top View)
Figure 4-2 RGT Package,
16-Pin VQFN With Exposed Thermal Pad
(Top View)
16-Pin VQFN With Exposed Thermal Pad
(Top View)
Table 4-1 Pin Functions
| PIN | TYPE | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| RHF (VQFN) | RGT (VQFN) | |||
| BIAS-1(1) | 23 | 15 | Input | Bias mode control, LSB |
| BIAS-2(1) | 24 | 16 | Input | Bias mode control, MSB |
| D1_IN– | 19 | 11 | Input | Amplifier D1 inverting input |
| D1_IN+ | 1 | 1 | Input | Amplifier D1 noninverting input |
| D1_OUT | 20 | 12 | Output | Amplifier D1 output |
| D2_IN– | 18 | 10 | Input | Amplifier D2 inverting input |
| D2_IN+ | 2 | 2 | Input | Amplifier D2 noninverting input |
| D2_OUT | 17 | 9 | Output | Amplifier D2 output |
| DGND(2) | 3 | 3 | Input | Ground reference for bias control pins |
| IADJ | 4 | 4 | Input | Bias current adjustment pin |
| NC | 6-16 | 6 | — | No internal connection |
| VCM | 5 | 5 | Output | Common-mode buffer output |
| VS– | 22 | 7, 14 | Power | Negative power-supply connection |
| VS+ | 21 | 8, 13 | Power | Positive power-supply connection |
| Thermal Pad | Pad | Pad | Power | Electrically connected to die substrate and VS–. Connect to VS– on the printed circuit board (PCB) for best performance. |
(1) The THS6222 defaults to the
shutdown (disable) state if a signal is not present on the bias pins.
(2) The DGND pin ranges from VS– to (VS+) – 5V.
Figure 4-3 YS Die,19-Pad Wafer Sale
(Top View)
Table 4-2 Bond Pad Functions
| PAD | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BIAS-1(1) | 18 | Input | Bias mode parallel control, LSB |
| BIAS-2(1) | 19 | Input | Bias mode parallel control, MSB |
| D1_IN– | 11 | Input | Amplifier D1 inverting input |
| D1_IN+ | 1 | Input | Amplifier D1 noninverting input |
| D1_OUT | 13 | Output | Amplifier D1 output (must be used for D1 output) |
| D1_OUT (OPT) | 12 | Output | Optional amplifier D1 output (pad can be left unconnected or connected to pad 13) |
| D2_IN– | 10 | Input | Amplifier D2 inverting input |
| D2_IN+ | 2 | Input | Amplifier D2 noninverting input |
| D2_OUT | 8 | Output | Amplifier D2 output (must be used for D2 output) |
| D2_OUT (OPT) | 9 | Output | Optional amplifier D2 output (can be left unconnected or connected to pad 8) |
| DGND(2) | 3 | Input | Ground reference for bias control pins |
| IADJ | 4 | Input | Bias-current adjustment pin |
| VCM | 5 | Output | Common-mode buffer output |
| VS– | 6, 16, 17 | Power | Negative power-supply connection |
| VS+ | 7, 14, 15 | Power | Positive power-supply connection |
| Backside | — | — | Connect to the lowest voltage potential on the die (generally VS–) |
(1) The THS6222 defaults to the shutdown
(disable) state if a signal is not present on the bias pins.
(2) The DGND pin ranges from VS– to (VS+) – 5V.