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ZHCSPU9 February 2024 TCAN1465-Q1 , TCAN1469-Q1

ADVANCE INFORMATION

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DMT|14
- MPSS087B
D|14
- MPDS177H

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

zhcspu9_oa

10.1 Register Maps

The TCAN146x-Q1 has a comprehensive register set with 7-bit addressing.

Table 10-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 10-1 should be considered as reserved locations and the register contents should not be modified.

Table 10-1 Device Registers

Address	Acronym	Register Name	Section
0h + formula	DEVICE_ID_y	Device Part Number	Section 10.1.1
8h	REV_ID_MAJOR	Major Revision	Section 10.1.2
9h	REV_ID_MINOR	Minor Revision	Section 10.1.3
Ah + formula	SPI_RSVD_x	SPI reserved registers	Section 10.1.4
Fh	Scratch_Pad_SPI	Read and Write Test Register SPI	Section 10.1.5
10h	MODE_CNTRL	Mode configurations	Section 10.1.6
11h	WAKE_PIN_CONFIG	WAKE pin configuration	Section 10.1.7
12h	PIN_CONFIG	Pin configuration	Section 10.1.8
13h	WD_CONFIG_1⁽¹⁾	Watchdog configuration 1	Section 10.1.9
14h	WD_CONFIG_2⁽¹⁾	Watchdog configuration 2	Section 10.1.10
15h	WD_INPUT_TRIG⁽¹⁾	Watchdog input trigger	Section 10.1.11
16h	WD_RST_PULSE⁽¹⁾	Watchdog output pulse width	Section 10.1.12
17h	FSM_CONFIG	Fail safe mode configuration	Section 10.1.13
18h	FSM_CNTR	Fail safe mode counter	Section 10.1.14
19h	DEVICE_RST	Device reset	Section 10.1.15
1Ah	DEVICE_CONFIG1	Device configuration	Section 10.1.16
1Bh	DEVICE_CONFIG2	Device configuration	Section 10.1.17
1Ch	SWE_EN	Sleep wake error timer enable	Section 10.1.18
29h	SDO_CONFIG	Enables SDO to also support the nINT function	Section 10.1.19
2Dh	WD_QA_CONFIG	Q and A Watchdog configuration	Section 10.1.20
2Eh	WD_QA_ANSWER	Q and A Watchdog answer	Section 10.1.21
2Fh	WD_QA_QUESTION	Q and A Watchdog question	Section 10.1.22
30h	SW_ID1⁽²⁾	Selective wake ID 1	Section 10.1.23
31h	SW_ID2⁽²⁾	Selective wake ID 2	Section 10.1.24
32h	SW_ID3⁽²⁾	Selective wake ID 3	Section 10.1.25
33h	SW_ID4⁽²⁾	Selective wake ID 4	Section 10.1.26
34h	SW_ID_MASK1⁽²⁾	Selective wake ID mask 1	Section 10.1.27
35h	SW_ID_MASK2⁽²⁾	Selective wake ID mask 2	Section 10.1.28
36h	SW_ID_MASK3⁽²⁾	Selective wake ID mask 3	Section 10.1.29
37h	SW_ID_MASK4⁽²⁾	Selective wake ID mask 4	Section 10.1.30
38h	SW_ID_MASK_DLC⁽²⁾	ID Mask, DLC and Data mask enable	Section 10.1.31
39h + formula	DATA_y⁽²⁾	CAN data byte 7 through 0	Section 10.1.32
41h + formula	SW_RSVD_y⁽²⁾	SW_RSVD0 through SW_RSVD4	Section 10.1.33
44h	SW_CONFIG_1⁽²⁾	CAN and CAN FD DR and behavior	Section 10.1.34
45h	SW_CONFIG_2⁽²⁾	Frame counter	Section 10.1.35
46h	SW_CONFIG_3⁽²⁾	Frame counter threshold	Section 10.1.36
47h	SW_CONFIG_4⁽²⁾	Mode configuration	Section 10.1.37
48h + formula	SW_CONFIG_RSVD_y⁽²⁾	SW_CONFIG_RSVD_0 through SW_CONFIG_RSVD_2	Section 10.1.38
4Bh	DEVICE_CONFIGx	Device configuration	Section 10.1.39
50h	INT_GLOBAL	Global Interrupts	Section 10.1.40
51h	INT_1	Interrupts	Section 10.1.41
52h	INT_2	Interrupts	Section 10.1.42
53h	INT_3	Interrupts	Section 10.1.43
54h	INT_CANBUS⁽¹⁾	CAN Bus fault interrupts	Section 10.1.44
55h	INT_GLOBAL_ENABLE	Interrupt enable for INT_GLOBAL	Section 10.1.45
56h	INT_ENABLE_1	Interrupt enable for INT_1	Section 10.1.46
57h	INT_ENABLE_2	Interrupt enable for INT_2	Section 10.1.47
58h	INT_ENABLE_3	Interrupt enable for INT_3	Section 10.1.48
59h	INT_ENABLE_CANBUS⁽¹⁾	Interrupt enable for INT_CANBUS	Section 10.1.49
5Ah + formula	INT_RSVD_y	Interrupt Reserved Register INT_RSVD0 through INT_RSVD5	Section 10.1.50

(1) TCAN1469-Q1

(2) TCAN1465-Q1 and TCAN1469-Q1

Complex bit access types are encoded to fit into small table cells. Table 10-2 shows the codes that are used for access types in this section.

Table 10-2 Device Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	H R	Set or cleared by hardware Read
Write Type
H	H	Set or cleared by hardware
W	W	Write
W1C	1C W	1 to clear Write
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.