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ZHCSQV1C March 2020 – December 2022 TCAN1463-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DYY|14
- MPSS114C
DMT|14
- MPSS087B
D|14
- MPDS177H

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

DMT|14
- QFND638

訂購(gòu)信息

7.8 Electrical Characteristics

Over recommended operating conditions with T_J = –40°C to 150°C, unless otherwise noted. All typical values are taken at 25°C, V_SUP = 12 V, V_IO = 3.3 V, V_CC = 5 V and R_L = 60 Ω

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
CAN Driver Characteristics
V_O(D)	Dominant output voltage Bus biasing active	CANH	TXD = 0 V, 50 ≤ R_L ≤ 65 ?, C_L = open, R_CM= open See Figure 8-1 and Figure 8-4	2.75		4.5	V
V_O(D)	Dominant output voltage Bus biasing active	CANL		0.5		2.25	V
V_O(R)	Recessive output voltage Bus biasing active		TXD = V_IO, R_L = open (no load), R_CM = open See Figure 8-1 and Figure 8-4	2		3	V
V_SYM	Driver symmetry Bus biasing active (V_O(CANH) + V_O(CANL)) / V_CC		nSTB= V_IO, R_L = 60 ?, C_SPLIT = 4.7 nF, C_L = Open, R_CM = Open, TXD = 250 kHz, 1 MHz, 2.5 MHz See Figure 8-1 and Figure 8-4	0.9		1.1	V/V
V_{SYM_DC}	DC Driver symmetry Bus biasing active V_CC – V_O(CANH) – V_O(CANL)		nSTB= V_IO, R_L = 60 ?, C_L = open See Figure 8-1 and Figure 8-4	–400		400	mV
V_OD(DOM)	Differential output voltage Bus biasing active Dominant	CANH - CANL	nSTB =V_IO, TXD = 0 V, 50 ? ≤ R_L ≤ 65 ?, C_L = open See Figure 8-1 and Figure 8-4	1.5		3	V
		CANH - CANL	nSTB =V_IO, TXD = 0 V, 45 ? ≤ R_L ≤ 70 ?, CL = open See Figure 8-1 and Figure 8-4	1.4		3.3	V
		CANH - CANL	nSTB =V_IO, TXD = 0 V, R_L = 2240 ?, C_L = open See Figure 8-1 and Figure 8-4	1.5		5	V
V_OD(REC)	Differential output voltage Bus biasing active Recessive	CANH - CANL	nSTB =V_IO, TXD = V_IO, R_L = open ?, C_L = open See Figure 8-1 and Figure 8-4	–50		50	mV
V_OD(STB)	Differential output voltage Bus biasing inactive Recessive	CANH	nSTB =0 V, TXD = V_IO, R_L = open (no load), C_L = open See Figure 8-1 and Figure 8-4	-0.1		0.1	V
		CANL	nSTB =0 V, TXD = V_IO, R_L = open (no load), C_L = open See Figure 8-1 and Figure 8-4	-0.1		0.1	V
		CANH - CANL	nSTB =0 V, TXD = V_IO, R_L = open (no load), C_L = open See Figure 8-1 and Figure 8-4	-0.2		0.2	V
I_OS(DOM)	Short-circuit steady-state output current Bus biasing active Dominant		nSTB = V_IO, TXD = 0 V -15 V ≤ V_(CANH) ≤ 40 V See Figure 8-1 and Figure 8-8	–100			mA
I_OS(DOM)			nSTB = V_IO,TXD = 0 V -15 V ≤ V_(CANL) ≤ 40 V See Figure 8-1 and Figure 8-8			100	mA
I_OS(REC)	Short-circuit steady-state output current Bus biasing active Recessive		nSTB = V_IO, V_BUS = CANH = CANL -27 V ≤ V_BUS ≤ 42 V See Figure 8-1 and Figure 8-8	–3		3	mA
R_ID(dom)	Differential input resistance in dominant phase		See Figure 9-2		40		ohm
R_{ID(active_rec)}	Differential input resistance in active recessive drive phase		See Figure 9-2		60		ohm
CAN Receiver Characteristics
V_IT(DOM)	Receiver dominant state input voltage range Bus biasing active		nSTB = V_IO, -12 V ≤ V_CM≤ 12 V See Figure 8-5 and Table 9-6	0.9		8	V
V_IT(REC)	Receiver recessive state input voltage range Bus biasing active			-3		0.5	V
V_HYS	Hysteresis voltage for input threshold Bus biasing active		nSTB = V_IO See Figure 8-5 and Table 9-6		135		mV
V_DIFF(DOM)	Receiver dominant state input voltage range Bus biasing inactive		nSTB = 0 V, -12 V ≤ V_CM≤ 12 V See Figure 8-5 and Table 9-6	1.150		8	V
V_DIFF(REC)	Receiver recessive state input voltage range Bus biasing inactive		nSTB = 0 V, -12 V ≤ V_CM≤ 12 V See Figure 8-5 and Table 9-6	-3		0.4	V
V_CM	Common mode range		nSTB = V_IO See Figure 8-5 and Table 9-6	–12		12	V
I_OFF(LKG)	Power-off (unpowered) bus input leakage current		V_SUP = 0 V, CANH = CANL = 5 V			2.5	μA
C_I	Input capacitance to ground (CANH or CANL) ⁽¹⁾		TXD = V_CC = V_IO			40	pF
C_ID	Differential input capacitance ⁽¹⁾		TXD = V_CC = V_IO			20	pF
R_ID	Differential input resistance		TXD = V_CC = V_IO = 5 V, nSTB = 5 V -12 V ≤ V_CM ≤ 12 V	30		100	k?
R_IN	Input resistance (CANH or CANL)		TXD = V_CC = V_IO = 5 V, nSTB = 5 V -12 V ≤ V_CM ≤ 12 V	15		50	k?
R_IN(M)	Input resistance matching: [1 – R_IN(CANH) / R_IN(CANL)] × 100%		V_(CANH) = V_(CANL)= 5 V	–3		3	%
R_CBF	Valid differential load impedance range for bus fault circuitry		R_CM = R_L, C_L = open	45		70	Ω
TXD Characteristics
V_IH	High-level input voltage			0.7			V_IO
V_IL	Low-level input voltage					0.3	V_IO
I_IH	High-level input leakage current		TXD = V_IO = 5.5 V	–2.5		1	μA
I_IL	Low-level input leakage current		TXD = 0 V, V_IO = 5.5 V	–115		–2.5	μA
I_LKG(OFF)	Unpowered leakage current		TXD = 5.5 V, V_SUP = V_IO = 0 V	–1		1	μA
R_PU	Pull-up resistance to V_IO			40	60	80	k?
C_I	Input Capacitance		V_IN = 0.4 x sin(2 × π × 2 × 10⁶ × t) + 2.5 V		5		pF
RXD Characteristics
V_OH	High-level output voltage		I_O = –2 mA See Figure 8-5	0.8			V_IO
V_OL	Low-level output voltage		I_O = 2 mA See Figure 8-5			0.2	V_IO
I_LKG(OFF)	Unpowered leakage current		RXD = 5.5 V, V_SUP = V_IO = 0 V	-1		1	μA
nSTB Characteristics
V_IH	High-level input voltage			0.7			V_IO
V_IL	Low-level input voltage					0.3	V_IO
I_IH	High-level input leakage current		nSTB = V_IO = 5.5 V	0.5		115	μA
I_IL	Low-level input leakage current		nSTB = 0 V, V_IO = 5.5 V	–1		1	μA
I_LKG(OFF)	Unpowered leakage current		nSTB = 5.5 V, V_IO = 0 V	–1		1	μA
R_PD	Pull-down resistance to GND			40	60	80	k?
nFAULT Characteristics
V_OH	High-level output voltage		I_O = -2 mA	0.8			V_IO
V_OL	Low-level output voltage		I_O = 2 mA			0.2	V_IO
I_LKG(OFF)	Unpowered leakage current		nFAULT = 5.5 V, V_IO = 0 V	–1		1	μA
INH_MASK Characteristics
V_IH	High-level input voltage			0.7			V_IO
V_IL	Low-level input voltage					0.3	V_IO
I_IH	High-level input leakage current		INH_MASK = V_CC = V_IO = 5.5 V	0.5		115	μA
I_IL	Low-level input leakage current		INH_MASK = 0 V, V_CC = V_IO = 5.5 V	-1		1	μA
I_LKG(OFF)	Unpowered leakage current		INH_MASK = 5.5 V, V_CC = V_IO = 0 V	-1		1	μA
R_PD	Pull-down resistance to GND ⁽¹⁾			40	60	80	k?
EN Characteristics
V_IH	High-level input voltage			0.7			V_IO
V_IL	Low-level input voltage					0.3	V_IO
I_IH	High-level input leakage current		EN = V_CC = V_IO = 5.5 V	0.5		115	μA
I_IL	Low-level input leakage current		EN = 0 V, V_CC = V_IO = 5.5 V	-1		1	μA
I_LKG(OFF)	Unpowered leakage current		EN = 5.5 V, V_CC = V_IO = 0 V	-1		1	μA
R_PD	Pull-down resistance to GND			40	60	80	k?
WAKE Characteristics
V_IH	High-level input voltage		Sleep mode	V_SUP - 2			V
V_IL	Low-level input voltage		Sleep mode			V_SUP - 3.5	V
I_IH	High-level input leakage current		WAKE = V_SUP – 1 V	-3			μA
I_IL	Low-level input leakage current		WAKE = 1 V			3	μA
INH Characteristics
ΔV_H	High-level voltage drop from V_SUP to INH (V_SUP- V_INH)		I_INH = –6 mA		0.5	1	V
I_LKG(INH)	Sleep mode leakage current		INH = 0 V	–0.5		0.5	μA
R_PD	Pull-down resistance		Sleep mode	2.5	4	5.6	M?

(1) Specified by design and verified via bench characterization