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ZHCSH19G November 2017 – December 2024 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

D|14
DMT|14

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.7 Electrical Characteristics

Over recommended operating conditions with T_A = –55°C to 125°C (unless otherwise noted).

PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
SUPPLY CHARACTERISTICS
I_SUP	Supply current V_SUP	Normal, Silent, Go-to-Sleep			40	70	μA
		Standby mode	Standby mode, V_CC > 4.5 V, V_IO > 2.8 V, V_INH = V_(WAKE) = V_SUP		15	45	μA
		Sleep mode	Sleep mode, V_CC = V_IO = V_INH = 0 V V_(WAKE) = V_SUP		15	30	μA
I_CC	Supply current Normal mode V_CC	Dominant	See Figure 7-2. TXD = 0 V, R_L = 60 ?, C_L = open. Typical bus load.			70	mA
		Dominant	See Figure 7-2. TXD = 0 V, R_L = 50 ?, C_L = open. High bus load.			80	mA
		Dominant with bus fault	See Figure 7-2. TXD = 0 V, CANH = -25 V, R_L = open, C_L = open			110	mA
		Recessive	See Figure 7-2. TXD = V_IO, R_L = 50 ?, C_L = open, R_CM = open			5	mA
	Supply current Silent and Go-to-Sleep mode		See Figure 7-2. TXD = V_IO, R_L = 50 ?, C_L = open			2.5	mA
	Supply current Standby mode		See Figure 7-2. EN = L, NSTB = L			5	μA
	Sleep mode		See Figure 7-2. EN = H or L, NSTB = L			5	μA
I_IO	I/O supply current	Normal mode	RXD floating, TXD = 0 V (dominant) nSTB = V_IO, EN = V_IO			450	μA
		Normal, Silent or Go-to-Sleep mode	RXD floating, TXD = V_IO recessive			5	μA
		Normal, Silent or Go-to-Sleep mode	RXD floating, TXD = V_IO recessive			5	μA
		Sleep mode	NSTB = L			5	μA
UV_SUP	Undervoltage detection on V_SUP for protected mode			3.0		4.2	V
V_HYS(UVSUP)	Hysteresis voltage on UV_SUP				50		mV
UV_VCC	Rising undervoltage detection on V_CC for protected mode				4.1	4.4	V
UV_VCC	Falling undervoltage detection on V_CC for protected mode			3.5	3.9		V
V_HYS(UVVCC)	Hysteresis voltage on UV_VCC				200		mV
UV_VIO	Undervoltage detection on V_IO for protected mode			1.3		2.75	V
V_HYS(UVIO)	Hysteresis voltage on UV_IO				80		mV
Driver Electrical Characteristics
V_O(D)	Bus output voltage dominant - normal mode	CANH	See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 50 ≤ R_L ≤ 65 ?, C_L = open, R_CM = open	2.75		4.5	V
V_O(D)	Bus output voltage dominant - normal mode	CANL		0.5		2.25	V
V_O(R)	Bus output voltage recessive	CANH and CANL	See Figure 7-2 and Figure 8-3, TXD = V_CC, V_IO = V_CC, Normal or Silent⁽²⁾, R_L = open, R_CM = open	2	0.5 × V_CC	3	V
V_OD(D)	Differential output voltage dominant	CANH - CANL	See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 50 ? ≤ R_L ≤ 65 ?, C_L = open, R_CM = open	1.5		3	V
			See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 45 ? ≤ R_L ≤ 50 ?, CL = open, R_CM = open	1.4		3	V
			See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, R_L = 2240 ?, C_L = open, R_CM = open	1.5		5	V
			See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 45 ? ≤ R_L ≤ 70 ?, C_L = open, R_CM = open	1.4		3.3	V
V_OD(R)	Differential output voltage recessive	CANH - CANL	See Figure 7-2 and Figure 8-3, TXD = V_CC, Normal or Silent mode⁽²⁾, R_L = 60 ?, C_L = open, R_CM = open	–120		12	mV
V_OD(R)	Differential output voltage recessive	CANH - CANL	See Figure 7-2 and Figure 8-3, TXD = V_CC, Normal or Silent mode⁽²⁾, R_L = open, C_L = open, R_CM = open	–50		50	mV
V_SYM	Driver symmetry, dominant or recessive V_SYM = (V_O(CANH) + V_O(CANL))/V_CC		See Figure 7-2 and Figure 9-4, Normal mode, C_L = open, R_CM = open, TXD = 1MHz⁽³⁾	0.9		1.1	V / V
V_{SYM_DC}	Driver symmetry, dominant V_SYM(DC) = V_CC - V_O(CANH) - V_O(CANL)		See Figure 7-2 and Figure 8-3, Normal or Silent mode, R_L = 60 ?, C_L = open, R_CM = open	–400		400	mV
I_OS(DOM)	Short circuit steady-state output current dominant		See Figure 7-10 and Figure 8-3, V_CANH = -5 V, CANL = open, TXD = 0 V	–100			mA
I_OS(DOM)	Short circuit steady-state output current dominant		See Figure 7-10 and Figure 8-3, V_CANL = 40 V, CANH = open, TXD = 0 V			100	mA
I_OS(REC)	Short circuit steady-state output current recessive		See Figure 7-10 and Figure 8-3 –27 V ≤ V_BUS ≤ 32 V, V_BUS = CANH = CANL, TXD = V_IO	–5		5	mA
V_O(STB)	Bus output voltage Standby mode	CANH	STB = V_CC or V_IO, R_L = open, R_CM = open	–0.1	0	0.1	V
		CANL		–0.1	0	0.1	V
		CANH - CANL		–0.2	0	0.2	V
Receiver Electrical Characteristics
V_CM	Common mode range Normal and Silent modes		See Figure 7-3 and Table 8-5	-30		30	V
V_IT	Input threshold voltage Normal and Silent modes		See Figure 7-3 and Table 8-5, V_CM ≤ ±20 V	500		900	mV
V_IT	Input threshold voltage Normal and Silent modes		See Figure 7-3 and Table 8-5, V_CM ≤ ±30 V	400		1000	mV
V_REC	Receiver recessive voltage		See Figure 7-3 and Table 8-5 Normal or Silent mode, V_CM = ±20 V	-3		0.5	V
V_DOM	Receiver dominant voltage			0.9		8	V
V_HYS	Hysteresis voltage for input threshold Normal and Silent modes		See Figure 7-3 and Table 8-5		120		mV
V_IT(Sleep)	Input threshold Sleep mode		See Figure 7-3 and Table 8-5; V_CM = ± 12 V	400		1150	mV
V_REC(Sleep)	Receiver recessive voltage Sleep mode			-3		0.4	V
V_DOM(Sleep)	Receiver dominant voltage Sleep mode			1.15		8	V
V_CM	Common mode range Standby, Go-to-Sleep and Sleep modes		See Figure 7-3 and Table 8-5	-12		12	V
I_IOFF(LKG)	Power-off (unpowered) bus input leakage current		CANH = CANL = 5 V, V_CC = GND, V_IO = GND, V_SUP = 0 V			4.8	μA
C_I	Input capacitance to ground (CANH or CANL)		TXD = V_CC, V_IO = V_CC⁽⁴⁾		24	30	pF
C_ID	Differential input capacitance (CANH or CANL)		TXD = V_CC, V_IO = V_CC⁽⁴⁾		12	15	pF
R_ID	Differential input resistance		TXD = V_CC = V_IO = 5 V, Normal mode; -30 ≤ V_CM ≤ +30V	30		80	k?
R_IN	Input resistance (CANH or CANL)		TXD = V_CC = V_IO = 5 V, Normal mode; -30 ≤ V_CM ≤ +30V	15		40	k?
R_IN(M)	Input resistance matching: [1 – R_IN(CANH) / R_IN(CANL)] × 100%		V_(CANH) = V_(CANL) = 5 V	–2%		2%
R_CBF	Valid differential load impedance range for bus fault circuitry		R_CM = R_L, C_L = open	45		70	Ω
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
V_IH	High level input voltage			0.7 V_IO			V
V_IL	Low level input voltage					0.3 V_IO	V
I_IH	High level input leakage current		TXD = V_CC = V_IO = 5.5 V	–2.5	0	1	μA
I_IL	Low level input leakage current		TXD = 0 V, V_CC = V_IO = 5.5 V	–100		–2.5	μA
I_LKG(OFF)	Unpowered leakage current		TXD = 5.5 V, V_CC = V_IO = 0 V	–1	0	1	μA
C_I	Input capacitance		V_IN = 0.4 x sin(2 x π x 2 x 10⁶ x t) + 2.5 V		5		pF
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
V_OH	High level output voltage		See Figure 7-3, I_O = –2 mA.	0.8 V_IO			V
V_OL	Low level output voltage		See Figure 7-3, I_O = –2 mA.			0.2 V_IO	V
nFAULT TERMINAL (FAULT AND STATUS OUTPUT)
V_OH	High level output voltage		See Figure 7-1, I_O = –2 mA.	0.8 V_IO			V
V_OL	Low level output voltage		See Figure 7-1 I_O = 2 mA.			0.2 V_IO	V
nSTB TERMINAL (STANDBY MODE INPUT)
V_IH	High level input voltage			0.7 V_IO			V
V_IL	Low level input voltage					0.3 V_IO	V
I_IH	High level input leakage current		nSTB = V_CC = V_IO = 5.5 V	0.5		10	μA
I_IL	Low level input leakage current		nSTB = 0 V, V_CC = V_IO = 5.5 V	–1		1	μA
I_LKG(OFF)	Unpowered leakage current		nSTB = 5.5 V, V_CC = 0 V, V_IO = 0 V	–1	0	1	μA
EN TERMINAL (ENABLE MODE INPUT)
V_IH	High level input voltage			0.7 V_IO			V
V_IL	Low level input voltage					0.3 V_IO	V
I_IH	High level input leakage current		EN = V_CC = V_IO = 5.5 V	0.5		10	μA
I_IL	Low level input leakage current		EN = 0 V, V_CC = V_IO = 5.5 V	–1		1	μA
I_LKG(OFF)	Unpowered leakage current		EN = 5.5 V, V_CC = 0 V, V_IO = 0 V	–1	0	1	μA
INH TERMINAL (INHIBIT OUTPUT)
ΔV_H	High level voltage drop INH with respect to V_SUP		I_INH = –0.5 mA		0.5	1	V
I_LKG(INH)	Leakage current		INH = 0 V, Sleep Mode	-5		5	μA
Wake TERMINAL (WAKE INPUT)
V_IH	High level input voltage		Standby and Sleep Mode	V_SUP - 1.9			V
V_IL	Low level input voltage		Standby and Sleep Mode			V_SUP - 3.5	V
I_IH	High level input current⁽⁵⁾		WAKE = V_SUP – 1 V	–25	–15		μA
I_IL	Low level input current⁽⁵⁾		WAKE = 1 V		15	25	μA

(1) All typical values are at 25°C and supply voltages of V_CC = 5 V, V_IO = 3.3 V, and R_L = 60 ?. Unless otherwise noted.

(2) The recessive bus voltage is the same if the device is in Normal mode with the nSTB and EN terminals high or if the device is in Silent mode with the nSTB terminal high and EN terminal low.

(3) The bus output voltage symmetry, V_SYM, is measured using R_TERM / 2 = 30 ? and C_SPLIT = 4.7 nF as shown in Figure 9-4

(4) Specified by design and verified during product validation using the ISO 11898-2 method.

(5) To minimize system level current consumption, the WAKE automatically configures itself based on the applied voltage to have
either an internal pull-up or pull-down current source. A high level input results in an internal pull-up and a low level input results in an
internal pull-down. For more information, refer to Section 8.4.6.2.