ZHCSN44B December 2021 – December 2023 SN75LVPE5421
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The SN75LVPE5421 has five 5-level inputs pins (EQ1, EQ0, GAIN, MODE, and RX_DET) that are used to control the configuration of the device. These 5-level inputs use a resistor divider to help set the 5 valid levels and provide a wider range of control settings. External resistors must be of 10% tolerance or better. The EQ0, EQ1, GAIN, and RX_DET pins are sampled at power-up only. The MODE pin can be exercised at device power up or in normal operation mode.
| LEVEL | SETTING |
|---|---|
| L0 | 1 k? to GND |
| L1 | 8.25 k? to GND |
| L2 | 24.9 k? to GND |
| L3 | 75 k? to GND |
| L4 | F (Float) |