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SLLS804D March 2009 – August 2016 SN65HVDA540-5-Q1 , SN65HVDA540-Q1 , SN65HVDA541-5-Q1 , SN65HVDA541-Q1 , SN65HVDA542-5-Q1 , SN65HVDA542-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

D|8
- MSOI002K

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾ ⁽²⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.3	6	V
V_IO	I/O supply voltage		–0.3	6	V
	Voltage at bus terminals (CANH, CANL)		–27	40	V
I_O	Receiver output current (RXD)			20	mA
V_I	Voltage input (TXD, STB, S)	HVDA54x	–0.3	6 V and V_I ≤ V_IO+ 0.3	V
V_I	Voltage input (TXD, STB, S)	HVDA54x-5	–0.3	6	V
T_J	Operating virtual-junction temperature		–40	150	°C
T_LEAD	Lead temperature (soldering, 10 seconds)			260	°C
T_stg	Storage temperature				°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	All pins except 6 and 7	±4000	V
		Human-body model (HBM), per AEC Q100-002⁽¹⁾	Pins 6 and 7⁽²⁾	±12000
		Charged-device model (CDM), per AEC Q100-011		±1000
		Machine model		±7000
		IEC 61000-4-2 contact discharge⁽³⁾	Pins 6 and 7 to pin 2	±7000

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) HBM test method based on AEC-Q100-002, CANH and CANL bus pins stressed with respect to each other and GND.

(3) IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system level configurations will lead to different results.

6.3 Recommended Operating Conditions

			MIN	MAX	UNIT
V_CC	Supply voltage		4.68	5.33	V
V_IO	I/O supply voltage		3	5.33	V
V_Ior V_IC	Voltage at any bus terminal (separately or common mode)		–12	12	V
V_IH	High-level input voltage	TXD, STB, S (for HVD54x-5: V_IO = V_CC)	0.7 × V_IO	V_IO	V
V_IL	Low-level input voltage	TXD, STB, S (for HVD54x-5: V_IO = V_CC)	0	0.3 × V_IO	V
V_ID	Differential input voltage, bus	Between CANH and CANL	–6	6	V
I_OH	High-level output current	RXD	–2		mA
I_OL	Low-level output current	RXD		2	mA
T_A	Operating ambient free-air temperature	See Thermal Information and Power Dissipation Ratings	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			HVDA54x, HVDA54x-5-Q1	UNIT
			D (SOIC)
			8 PINS
R_θJA	Junction-to-ambient thermal resistance	Low-K thermal resistance	140	°C/W
R_θJA	Junction-to-ambient thermal resistance	High-K thermal resistance	112	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		56	°C/W
R_θJB	Junction-to-board thermal resistance		50	°C/W
ψ_JT	Junction-to-top characterization parameter		13	°C/W
ψ_JB	Junction-to-board characterization parameter		55	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating conditions, T_J = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices V_IO = V_CC

PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
SUPPLY CHARACTERISTICS (HVDA54x)
I_CC	5-V supply current	Standby mode (HVDA540/541 Only)	STB at V_IO, V_CC = 5.33 V, V_IO = 3 V, TXD at V_IO ⁽²⁾			5	µA
		Normal mode (Dominant)	TXD at 0 V, 60-Ω load, STB / S at 0 V		50	70	mA
		Normal mode (Recessive)	TXD at V_IO, No load, STB / S at 0 V or S at V_IO		5.5	10
		Silent Mode (HVDA542 only)	TXD at V_IO, No load, STB / S at 0 V or S at V_IO		5.5	10
I_IO	I/O supply current	Standby mode (HVDA540/541 Only)	STB at V_IO, V_CC = 5.33 V or 0 V, RXD floating, TXD at V_IO T_A = –40°C, 25°C, 125°C⁽³⁾		7	15	µA
I_IO	I/O supply current	Normal mode (recessive or dominant) and Silent Mode (HVDA542 Only)	V_CC = 5.33 V, RXD floating, TXD at 0 V or V_IO. Normal Mode: STB or S at 0 V. Silent Mode (HVDA542): S at V_IO.		75	300	µA
UV_VCC	Undervoltage detection on V_CC for forced standby mode			3.2	3.6	4	V
V_HYS(UVVCC)	Hysteresis voltage for undervoltage detection on UV_VCC for standby mode				200		mV
UV_VIO	Undervoltage detection on V_IO for forced standby mode			1.9	2.45	2.95	V
V_HYS(UVVIO)	Hysteresis voltage for undervoltage detection on UV_VIO for forced standby mode				130		mV
SUPPLY CHARACTERISTICS (HVDA54x-5)
I_CC	5-V supply current	Standby mode (HVDA540-5/541-5 Only)	STB at V_CC, V_CC = 5.33 V, TXD at V_CC ⁽²⁾			20	µA
		Normal mode (Dominant)	TXD at 0 V, 60-Ω load, STB / S at 0 V		50	70	mA
		Normal mode (Recessive)	TXD at V_IO, No load, STB / S at 0 V or S at V_IO		5.5	10
		Silent Mode (HVDA542 only)	TXD at V_IO, No load, STB / S at 0 V or S at V_IO		5.5	10
UV_VCC	Undervoltage detection on V_CC for forced standby mode			3.2	3.6	4	V
V_HYS(UVVCC)	Hysteresis voltage for undervoltage detection on UV_VCC for standby mode				240		mV
DEVICE SWITCHING CHARACTERISTICS: PROPAGATION TIME (LOOP TIME TXD TO RXD)
t_PROP(LOOP1)	Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant		Figure 9, STB at 0 V	70		230	ns
t_PROP(LOOP2)	Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive		Figure 9, STB at 0 V	70		230	ns
DRIVER ELECTRICAL CHARACTERISTICS
V_O(D)	Bus output voltage (dominant)	CANH	V_I= 0 V, STB / S at 0 V, R_L = 60 Ω, See Figure 2 and Figure 15	2.9		4.5	V
V_O(D)	Bus output voltage (dominant)	CANL		0.8		1.75	V
V_O(R)	Bus output voltage (recessive)		V_I = V_IO, V_IO = 3 V, STB at 0 V or S at X⁽⁴⁾, R_L = 60 Ω, See Figure 2 and Figure 15	2	2.5	3	V
V_O(STBY)	Bus output voltage, standby mode (HVDA540, HVDA541 only)		STB / S at V_IO, R_L = 60 Ω, See Figure 2 and Figure 15	–0.1		0.1	V
V_OD(D)	Differential output voltage (dominant)		V_I = 0 V, R_L = 60 Ω, STB / S at 0 V, See Figure 2, Figure 15, and Figure 3	1.5		3	V
V_OD(D)	Differential output voltage (dominant)		V_I = 0 V, R_L = 45 Ω, STB / S at 0 V, See Figure 2, Figure 15, and Figure 3	1.4		3	V
V_OD(R)	Differential output voltage (recessive)		V_I = 3 V, STB / S at 0 V, R_L = 60 Ω, See Figure 2 and Figure 15	–0.012		0.012	V
V_OD(R)	Differential output voltage (recessive)		V_I = 3 V, STB / S at 0 V, No load	–0.5		0.05	V
V_SYM	Output symmetry (dominant or recessive) (V_O(CANH) + V_O(CANL))		STB / S at 0 V, R_L = 60 Ω, See Figure 12	0.9 V_CC	V_CC	1.1 V_CC	V
V_OC(SS)	Steady-state common-mode output voltage		STB / S at 0 V, R_L = 60 Ω, See Figure 8	2	2.5	3	V
ΔV_OC(SS)	Change in steady-state common-mode output voltage		STB / S at 0 V, R_L = 60 Ω, See Figure 8		40		mV
I_{OS(SS)_DOM}	Short-circuit steady-state output current, Dominant		V_CANH = 0 V, CANL open, TXD = low, See Figure 11	–100			mA
I_{OS(SS)_DOM}	Short-circuit steady-state output current, Dominant		V_CANL = 32 V, CANH open, TXD = low, See Figure 11			100	mA
I_{OS(SS)_REC}	Short-circuit steady-state output current, Recessive		–20 V ≤ V_CANH ≤ 32 V, CANL open, TXD = high, See Figure 11	–10		10	mA
I_{OS(SS)_REC}	Short-circuit steady-state output current, Recessive		–20 V ≤ V_CANL ≤ 32 V, CANH open, TXD = high, See Figure 11	–10		10	mA
C_O	Output capacitance		See receiver input capacitance
DRIVER SWITCHING CHARACTERISTICS
t_PLH	Propagation delay time, low-to-high level output		STB / S at 0 V, See Figure 4		65		ns
t_PHL	Propagation delay time, high-to-low level output		STB / S at 0 V, See Figure 4		50		ns
t_R	Differential output signal rise time		STB / S at 0 V, See Figure 4		25		ns
t_F	Differential output signal fall time		STB / S at 0 V, See Figure 4		55		ns
t_EN	Enable time from standby or silent mode to normal mode dominant		See Figure 7			20	µs
t_(DOM)⁽⁵⁾	Dominant time out		See Figure 10	300	400	700	µs
RECEIVER ELECTRICAL CHARACTERISTICS
V_IT+	Positive-going input threshold voltage, normal mode		STB / S at 0 V, See Table 1		800	900	mV
V_IT–	Negative-going input threshold voltage, normal mode		STB / S at 0 V, See Table 1	500	650		mV
V_hys	Hysteresis voltage (V_IT+ – V_IT–)			100	125		mV
V_IT(STBY)	Input threshold voltage, standby mode (HVDA541 only)		STB at V_IO	400		1150	mV
I_{I(OFF_LKG)}	Power-off (unpowered) bus input leakage current		CANH = CANL = 5 V, V_CC at 0 V, V_IO at 0 V, TXD at 0 V			3	µA
C_I	Input capacitance to ground (CANH or CANL)		HVDA54x: TXD at V_IO, V_IO at 3.3 V. HVDA54x-5: TXD at V_CC V_I = 0.4 sin (4E6πt) + 2.5 V		13		pF
C_ID	Differential input capacitance		HVDA54x: TXD at V_IO, V_IO at 3.3 V. HVDA54x-5: TXD at V_CC V_I = 0.4 sin(4E6πt)		5		pF
R_ID	Differential input resistance		HVDA54x: TXD at V_IO, V_IO = 3.3 V, STB at 0 V HVDA54x-5: TXD at V_CC, STB at 0 V	29		80	kΩ
R_IN	Input resistance (CANH or CANL)			14.5	25	40	kΩ
R_I(M)	Input resistance matching [1 – ®_IN(CANH)/R_IN(CANL))] × 100%		V_(CANH) = V_(CANL)	–3	0	3	%
RECEIVER SWITCHING CHARACTERISTICS
t_PLH	Propagation delay time, low-to-high-level output		STB / S at 0 V , See Figure 6		95		ns
t_PHL	Propagation delay time, high-to-low-level output		STB / S at 0 V , See Figure 6		60		ns
t_R	Output signal rise time		STB / S at 0 V , See Figure 6		13		ns
t_F	Output signal fall time		STB / S at 0 V , See Figure 6		10		ns
t_BUS	Dominant time required on bus for wake-up from standby (HVDA541 only)		STB at V_IO, See Figure 17 and Figure 18	1.5		5	µs
t_CLEAR	Recessive time on the bus to clear the standby mode receiver output (RXD) if standby mode is entered while bus is dominant (HVDA541 only)		STB at V_IO, See Figure 17 and Figure 18	1.5		5	µs
TXD PIN CHARACTERISTICS
V_IH	High-level input voltage		HVD54x-5: V_IO = V_CC	0.7 × V_IO			V
V_IL	Low-level input voltage		HVD54x-5: V_IO = V_CC			0.3 × V_IO	V
I_IH	High-level input current		HVDA54x: TXD at V_IO HVDA54x-5: TXD at V_CC	–2		2	µA
I_IL	Low-level input current		TXD at 0 V	–100		–7	µA
RXD PIN CHARACTERISTICS
V_OH	High-level output voltage		I_O = –2 mA, See Figure 6 HVD54x-5: V_IO = V_CC	0.8 × V_IO			V
V_OL	Low-level output voltage		I_O = 2 mA, See Figure 6 HVD54x-5: V_IO = V_CC			0.2 × V_IO	V
STB PIN CHARACTERISTICS (HVDA540 AND HVDA541 ONLY)
V_IH	High-level input voltage		HVD54x-5: V_IO = V_CC	0.7 × V_IO			V
V_IL	Low-level input voltage		HVD54x-5: V_IO = V_CC			0.3 × V_IO	V
I_IH	High-level input current		HVDA54x: STB at V_IO HVDA54x-5: STB at V_CC	–2		2	µA
I_IL	Low-level input current		STB at 0 V	–20			µA
S PIN CHARACTERISTICS (HVDA542 ONLY)
V_IH	High-level input voltage		HVD54x-5: V_IO = V_CC	0.7 × V_IO			V
V_IL	Low-level input voltage		HVD54x-5: V_IO = V_CC			0.3 × V_IO	V
I_IH	High-level input current		HVDA54x: S at V_IO HVDA54x-5: S at V_CC			30	µA
I_IL	Low-level input current		S at 0 V	–2		2	µA
	Thermal shutdown temperature				185		°C

(1) All typical values are at 25°C and supply voltages of V_CC = 5 V and V_IO = 3.3 V.

(2) The V_CC supply is not needed during standby mode so in the application I_CC in standby mode may be zero. If the V_CC supply remains, then I_CC is per specification with V_CC.

(3) See SN65HVDA54x-Q1 Errata .

(4) For the HVDA542 device the bus output voltage (recessive) will be the same if the device is in normal mode with S pin at 0 V or if the device is in silent mode with the S pin at HIGH.

(5) The TXD dominant time out (t_(DOM)) disables the driver of the transceiver once the TXD has been dominant longer than t_(DOM), which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_(DOM) minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t_(DOM) = 11 bits / 300 µs = 37 kbps

6.6 Power Dissipation Ratings

over recommended operating conditions, T_J = –40°C to 150°C (unless otherwise noted), HVDA54x-5 devices V_IO = V_CC

			MIN	TYP	MAX	UNIT
P_D	Average power dissipation	V_CC = 5 V, V_IO = V_CC, T_J = 27°C, R_L = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, C_L at RXD = 15 pF		140		mW
P_D	Average power dissipation	V_CC = 5.33 V, V_IO = V_CC, T_J = 130°C, R_L = 60 Ω, STB at 0 V, Input to TXD at 500 kHz, 50% duty cycle square wave, C_L at RXD = 15 pF			215	mW

6.7 Typical Characteristics

SN65HVDA540-Q1 SN65HVDA541-Q1 SN65HVDA542-Q1 SN65HVDA540-5-Q1 SN65HVDA541-5-Q1 SN65HVDA542-5-Q1 C001_SLLS804.png

	STB = 0 V RL= 60 Ω CL= Open Rcm= open Temp = 25°C

Figure 1. HVDA540 V_CC vs V_OD from 4.5 V to 5.5 V