ZHCSFG5A September 2016 – November 2016 SN65HVD233-Q1 , SN65HVD234-Q1 , SN65HVD235-Q1
PRODUCTION DATA.
Figure 12. Driver Voltage, Current, and Test Definition
Figure 13. Bus Logic State Voltage Definitions
Figure 14. Driver VOD
Figure 16. Receiver Voltage and Current Definitions
| INPUT | OUTPUT | MEASURED | ||
|---|---|---|---|---|
| VCANH | VCANL | RXD | |VID| | |
| –6.1 V | –7 V | L | VOL | 900 mV |
| 12 V | 11.1 V | L | 900 mV | |
| –1 V | –7 V | L | 6 V | |
| 12 V | 6 V | L | 6 V | |
| –6.5 V | –7 V | H | VOH | 500 mV |
| 12 V | 11.5 V | H | 500 mV | |
| –7 V | –1 V | H | 6 V | |
| 6 V | 12 V | H | 6 V | |
| Open | Open | H | X | |
NOTE:
This test is conducted to test survivability only. Data stability at the RXD output is not specified.
NOTE:
All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 20. ten(z) Test Circuit and Voltage Waveforms
Figure 21. VOC(pp) Test Circuit and Voltage Waveforms
Figure 22. t(loop) Test Circuit and Voltage Waveforms
Figure 23. t(LBK) Test Circuit and Voltage Waveforms
Figure 24. t(AB1) Test Circuit and Voltage Waveforms
Figure 25. t(AB2) Test Circuit and Voltage Waveforms
Figure 26. IOS Test Circuit and Waveforms
NOTE:
All input pulses are supplied by a generator with f ≤ 1.5 MHz.
Figure 28. Equivalent Input and Output Schematic Diagrams