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SLLS545G November 2002 – October 2015 SN55HVD251 , SN65HVD251

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

DRJ|8
- MPDS153B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

DRJ|8
- QFND085E

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

			MIN	MAX	UNIT
Supply voltage, V_CC			–0.3	7	V
Voltage at any bus pin(CANH or CANL)			–36	36	V
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b		CANH, CANL	–200	200	V
Input voltage, V_I (D, Rs, or R)			–0.3	V_CC + 0.5	V
Receiver output current, I_O			–10	10 mA	mA
Electrical fast transient/burst	IEC 61000-4-4, Classification B	CANH, CANL	–3	3	kV
Continuous total power dissipation			(see Dissipation Ratings)

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground pin.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±6000	V
		Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	CANH, CANL and GND	±14000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	MAX	UNIT
Supply voltage, V_CC		4.5	5.5	V
Voltage at any bus terminal (separately or common mode) V_I or V_IC		–7⁽¹⁾	12	V
High-level input voltage, V_IH	D input	0.7 V_CC		V
Low-level input voltage, V_IL	D input		0.3 V_CC	V
Differential input voltage, V_ID		–6	6	V
Input voltage to Rs, V_I(Rs)		0	V_CC	V
Input voltage at Rs for standby, V_I(Rs)		0.75 V_CC	V_CC	V
Rs wave-shaping resistance		0	100	kΩ
High-level output current, I_OH	Driver	–50		mA
High-level output current, I_OH	Receiver	–4		mA
Low-level output current, I_OL	Driver		50	mA
Low-level output current, I_OL	Receiver		4	mA
Operating free-air temperature, T_A	SN65HVD251	–40	125	°C
Operating free-air temperature, T_A	SN55HVD251	–55	125	°C
Junction temperature, T_J			145	°C

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		SN55HVD251	SN65HVD251		UNIT
		DRJ (SON)	D (SOIC)	P (PDIP)
		8 PINS	8 PINS	8 PINS
R_θJC(top)	Junction-to-case (top) thermal resistance	52	44.6	66.6	°C/W
R_θJB	Junction-to-board thermal resistance	73	78.7	48.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Supply Current

over operating free-air temperature range (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MAX	UNIT
I_CC	Supply current	Standby	Rs at V_CC, D at V_CC	275	µA
		Dominant	D at 0 V, 60-Ω load, Rs at 0 V	65	mA
		Recessive	D at V_CC, no load, Rs at 0 V	14	mA

(1) All typical values are at 25°C and with a 5-V supply.

6.6 Electrical Characteristics: Driver

over recommended operating conditions (unless otherwise noted).

PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
V_O(D)	Bus output voltage (Dominant)	CANH	Figure 10 and Figure 11 , D at 0 V Rs at 0 V, T ≥ –40°C	2.75	3.5	4.5	V
V_O(D)	Bus output voltage (Dominant)	CANL	Figure 10 and Figure 11 , D at 0 V Rs at 0 V, T ≥ –40°C	0.5		2
V_O(R)	Bus output voltage (Recessive)	CANH	Figure 10 and Figure 11 , D at 0.7 V_CC, Rs at 0 V	2	2.5	3
V_O(R)	Bus output voltage (Recessive)	CANL	Figure 10 and Figure 11 , D at 0.7 V_CC, Rs at 0 V	2	2.5	3
V_OD(D)	Differential output voltage (Dominant)		Figure 10 , D at 0 V, Rs at 0 V	1.5	2	3	V
			Figure 12 , D at 0 V, Rs at 0 V, R_NODE = 330 Ω	1.2	2	3.1	V
			Figure 12 , D at 0 V, Rs at 0 V, R_NODE = 165 Ω, V_CC ≥ 4.75 V	1.2	2	3.1	V
V_OD(R)	Differential output voltage (Recessive)		Figure 10 and Figure 11 , D at 0.7 V_CC	–120		12	mV
V_OD(R)	Differential output voltage (Recessive)		D at 0.7 V_CC, no load, T ≤ 85°C	–0.5		0.05	V
V_OC(pp)	Peak-to-peak common-mode output voltage		Figure 18, Rs at 0 V		600		mV
I_IH	High-level input current, D Input		D at 0.7 V_CC	–40		0	µA
I_IL	Low-level input current, D Input		D at 0.3 V_CC	–60		0	µA
I_OS(SS)	Short-circuit steady-state output current		Figure 20, V_CANH at –7 V, CANL Open	–200			mA
			Figure 20, V_CANH at 12 V, CANL Open			2.5
			Figure 20, V_CANL at -7 V, CANH Open	–2
			Figure 20, V_CANL at 12 V, CANH Open			200
C_O	Output capacitance		See receiver input capacitance
I_OZ	High-impedance output current		See receiver input current
I_IRs(s)	Rs input current for standby		Rs at 0.75 V_CC	–10			µA
I_IRs(f)	Rs input current for full speed operation		Rs at 0 V	–550		0	µA

(1) All typical values are at 25°C and with a 5-V supply.

6.7 Electrical Characteristics: Receiver

over recommended operating conditions (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IT+	Positive-going input threshold voltage	Rs at 0 V, (See Table 1)			750	900	mV
V_IT-	Negative-going input threshold voltage			500	650
V_hys	Hysteresis voltage (V_IT+- V_IT-)				100
V_OH	High-level output voltage	Figure 15, I_O = –4 mA		0.8 V_CC			V
V_OL	Low-level output voltage	Figure 15, I_O = 4 mA				0.2 V_CC	V
I_I	Bus input current	CANH or CANL at 12 V	Other bus pin at 0 V, Rs at 0 V, D at 0.7 V_CC			600	µA
		CANH or CANL at 12 V, V_CCat 0 V				715
		CANH or CANL at -7 V		–460
		CANH or CANL at -7 V, V_CCat 0 V		–340
C_I	Input capacitance, (CANH or CANL)	Pin-to-ground, V_I = 0.4 sin (4E6πt) + 0.5 V, D at 0.7 V_CC			20		pF
C_ID	Differential input capacitance	Pin-to-pin, V_I = 0.4 sin (4E6πt) + 0.5 V, D at 0.7 V_CC			10		pF
R_ID	Differential input resistance	D at 0.7 V_CC, Rs at 0 V		40		100	kΩ
R_IN	Input resistance, (CANH or CANL)	D at 0.7 V_CC, Rs at 0 V		20		50	kΩ
	Receiver noise rejection	See Figure 22

6.8 VREF-Pin Characteristics

over recommended operating conditions (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_O	Reference output voltage	–5 µA < I_O < 5 µA	0.45 V_CC		0.55 V_CC	V
V_O	Reference output voltage	–50 µA < I_O < 50 µA	0.4 V_CC		0.6 V_CC	V

6.9 Power Dissipation Characteristics

PARAMETER		TEST CONDITIONS	TYP	UNIT
P_D	Device power dissipation	V_CC = 5 V, Tj = 27°C, RL = 60 Ω, R_S at 0 V, Input to D a 500-kHz 50% duty cycle square wave	97.7	mW
P_D	Device power dissipation	V_CC = 5.5 V, Tj = 130°C, RL = 60 Ω, R_S at 0 V, Input to D a 500-kHz 50% duty cycle square wave	142	mW
T_SD	Thermal shutdown junction temperature		165	°C

6.10 Switching Characteristics: Driver

over recommended operating conditions (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_pLH	Propagation delay time, low-to-high-level output	Figure 13, Rs at 0 V		40	70
		Figure 13, Rs with 10 kΩ to ground		90	125
		Figure 13, Rs with 100 kΩ to ground		500	800
t_pHL	Propagation delay time, high-to-low-level output	Figure 13, Rs at 0 V		85	125
		Figure 13, Rs with 10 kΩ to ground		200	260
		Figure 13, Rs with 100 kΩ to ground		1150	1450
t_sk(p)	Pulse skew (\|t_pHL - t_pLH\|)	Figure 13, Rs at 0 V		45	85
		Figure 13, Rs with 10 kΩ to ground		110	180	ns
		Figure 13, Rs with 100 kΩ to ground		650	900
t_r	Differential output signal rise time	Figure 13, Rs at 0 V	35	80	100
t_f	Differential output signal fall time	Figure 13, Rs at 0 V	35	80	100
t_r	Differential output signal rise time	Figure 13, Rs with 10 kΩ to ground	100	150	250
t_f	Differential output signal fall time	Figure 13, Rs with 10 kΩ to ground	100	150	250
t_r	Differential output signal rise time	Figure 13, Rs with 100 kΩ to ground	600	950	1550
t_f	Differential output signal fall time	Figure 13, Rs with 100 kΩ to ground	600	950	1550
t_en	Enable time from standby to dominant	Figure 17			0.5	µs

6.11 Switching Characteristics: Device

over recommended operating conditions (unless otherwise noted).

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_loop1	Total loop delay, driver input to receiver output, recessive to dominant	Figure 19, Rs at 0 V	60	100	ns
		Figure 19, Rs with 10 kΩ to ground	100	150
		Figure 19, Rs with 100 kΩ to ground	440	800
t_loop2	Total loop delay, driver input to receiver output, dominant to recessive	Figure 19, Rs at 0 V	115	150	ns
		Figure 19, Rs with 10 kΩ to ground	235	290
		Figure 19, Rs with 100 kΩ to ground	1070	1450
t_loop2	Total loop delay, driver input to receiver output, dominant to recessive	Figure 19, Rs at 0 V, V_CC from 4.5 V to 5.1 V	105	145	ns

6.12 Switching Characteristics: Receiver

over recommended operating conditions (unless otherwise noted).

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_pLH	Propagation delay time, low-to-high-level output	Figure 15	35	50
t_pHL	Propagation delay time, high-to-low-level output		35	50
t_sk(p)	Pulse skew (\|t_pHL - t_pLH\|)			20	ns
t_r	Output signal rise time		2	4	ns
t_f	Output signal fall time		2	4
t_p(sb)	Propagation delay time in standby	Figure 21, Rs at V_CC		500

6.13 Dissipation Ratings

PACKAGE	CIRCUIT BOARD MODEL	T_A = 25°C POWER RATING	DERATING FACTOR ⁽¹⁾ ABOVE T_A = 25°C	T_A = 85°C POWER RATING	T_A = 125°C POWER RATING
SOIC (D)	Low-K⁽²⁾	576 mW	4.8 mW/°C	288 mW	96 mW
SOIC (D)	High-K⁽³⁾	924 mW	7.7 mW/°C	462 mW	154 mW
PDIP (P)	Low-K⁽²⁾	888 mW	7.4 mW/°C	444 mW	148 mW
PDIP (P)	High-K⁽³⁾	1212 mW	10.1 mW/°C	606 mW	202 mW
WSON (DRJ)	Low-K⁽²⁾	403 mW	4.03 mW/°C	262 mW	100 mW
	High-K (no Vias)⁽³⁾	1081 mW	10.8 mW/°C	703 mW	270 mW
	High-K (with Vias)	2793 mW	27.9 mW/°C	1815 mW	698 mW