ZHCSOD3F December 1982 – June 2021 SN54HC74 , SN74HC74
PRODUCTION DATA
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | D, DB, N, NS, PW, J, or W | FK | ||
| 1 CLR | 1 | 2 | Input | Channel 1, Clear Input, Active Low |
| 1D | 2 | 3 | Input | Channel 1, Data Input |
| 1CLK | 3 | 4 | Input | Channel 1, Positive edge triggered clock input |
| 1 PRE | 4 | 6 | Input | Channel 1, Preset Input, Active Low |
| 1Q | 5 | 8 | Output | Channel 1, Output |
| 1 Q | 6 | 9 | Output | Channel 1, Inverted Output |
| GND | 7 | 10 | — | Ground |
| 2 Q | 8 | 12 | Output | Channel 2, Inverted Output |
| 2Q | 9 | 13 | Output | Channel 2, Output |
| 2 PRE | 10 | 14 | Input | Channel 2, Preset Input, Active Low |
| 2CLK | 11 | 16 | Input | Channel 2, Positive edge triggered clock input |
| 2D | 12 | 18 | Input | Channel 2, Data Input |
| 2 CLR | 13 | 19 | Input | Channel 2, Clear Input, Active Low |
| VCC | 14 | 20 | — | Positive Supply |
| NC | 1, 5, 7, 11, 15, 17 | — | Not internally connected | |