ZHCSIM2D June 2010 – August 2021 PCM9211
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| RST PIN DEVICE RESET REQUIREMENTS, Figure 7-1 | |||||
| tRSTL | RST pulse width ( RST pin = low) | 1 | μs | ||
| ADC SYSTEM CLOCK INPUT(1), Figure 7-3 | |||||
| tSCY | System clock cycle time | 30 | ns | ||
| tSCH | System clock high time | 0.4 tSCY | ns | ||
| tSCL | System clock low time | 0.4 tSCY | ns | ||
| System clock duty cycle | 40% | 60% | |||
| AUDIO DATA INTERFACE, SLAVE MODE(2), Figure 7-5 | |||||
| tBCY | BCK cycle time | 75 | ns | ||
| tBCH | BCK high time | 35 | ns | ||
| tBCL | BCK low time | 35 | ns | ||
| tLRS | LRCK setup time to BCK rising edge | 10 | ns | ||
| tLRH | LRCK hold time to BCK rising edge | 10 | ns | ||
| tDOD | DOUT delay time from BCK falling edge | 10 | 70 | ns | |
| AUDIO DATA INTERFACE, MASTER MODE(2), Figure 7-6 | |||||
| tBCY | BCK cycle time | 1/64fS | |||
| tBCH | BCK high time | 0.4 tBCY | 0.5 tBCY | 0.6 tBCY | |
| tBCL | BCK low time | 0.4 tBCY | 0.5 tBCY | 0.6 tBCY | |
| tLRD | LRCK delay time to BCK falling edge | 0 | 30 | ns | |
| tDOD | DOUT delay time from BCK falling edge | 0 | 30 | ns | |
| LATENCY BETWEEN INPUT BIPHASE AND LRCKO/DOUT, Figure 7-12 | |||||
| tLATE | LRCKO/DOUT latency | 4/fS | s | ||
| DIR DECODED AUDIO DATA OUTPUT(3), Figure 7-13 | |||||
| tSCY | System clock pulse cycle time | 18 | ns | ||
| tCKLR | Delay time of BCKO falling edge to LRCKO valid | –10 | 10 | ns | |
| tBCY | BCKO pulse cycle time | 1/64fS | s | ||
| tBCH | BCKO pulse width high | 60 | ns | ||
| tBCL | BCKO pulse width low | 60 | ns | ||
| tBCDO | Delay time of BCKO falling edge to DOUT valid | –10 | 10 | ns | |
| tR | Rising time of all signals | 5 | ns | ||
| tF | Falling time of all signals | 5 | ns | ||
| CONTROL INTERFACE REQUIREMENTS, FOUR WIRE SCI, Figure 7-29 | |||||
| tMCY | MC Pulse cycle time | 100 | ns | ||
| tMCL | MC Low level time | 40 | ns | ||
| tMCH | MC High level time | 40 | ns | ||
| tMHH | MS High level time | tMCY | ns | ||
| tMSS | MS Falling edge to MC rising edge | 30 | ns | ||
| tMSH | MS Rising edge from MC rising edge for LSB | 15 | ns | ||
| tMDH | MDI Hold time | 15 | ns | ||
| tMDS | MDI Set-up time | 15 | ns | ||
| tMDD | MDO Enable or delay time from MC falling edge | 0 | 30 | ns | |
| tMDR | MDO Disable time from MS rising edge | 0 | 30 | ns | |
| CONTROL INTERFACE, SCL AND SDA, STANDARD MODE, Figure 7-33 | |||||
| fSCL | SCL clock frequency | 100 | kHz | ||
| tBUF | Bus free time between STOP and START condition | 4.7 | μs | ||
| tLOW | Low period of the SCL clock | 4.7 | μs | ||
| tHI | High period of the SCL clock | 4 | μs | ||
| tS-SU | Setup time for START/Repeated START condition | 4.7 | μs | ||
| tS-HD | Hold time for START/Repeated START condition | 4 | μs | ||
| tD-SU | Data setup time | 250 | ns | ||
| tD-HD | Data hold time | 0 | 3450 | ns | |
| tSCL-R | Rise time of SCL signal | 1000 | ns | ||
| tSCL-F | Fall time of SCL signal | 1000 | ns | ||
| tSDA-R | Rise time of SDA signal | 1000 | ns | ||
| tSDA-F | Fall time of SDA signal | 1000 | ns | ||
| tP-SU | Setup time for STOP condition | 4 | μs | ||
| tGW | Allowable glitch width | NA | ns | ||
| CB | Capacitive load for SDA and SCL line | 400 | pF | ||
| VNH | Noise margin at High level for each connected device (including hysteresis) | 0.2 × VDD | V | ||
| VNL | Noise margin at Low level for each connected device (including hysteresis) | 0.1 × VDD | V | ||
| VHYS | Hysteresis of Schmitt-trigger input | NA | V | ||
| CONTROL INTERFACE, SCL AND SDA, FAST MODE, Figure 7-33 | |||||
| fSCL | SCL clock frequency | 400 | |||
| tBUF | Bus free time between STOP and START condition | 1.3 | |||
| tLOW | Low period of the SCL clock | 1.3 | |||
| tHI | High period of the SCL clock | 0.6 | |||
| tS-SU | Setup time for START/Repeated START condition | 0.6 | |||
| tS-HD | Hold time for START/Repeated START condition | 0.6 | |||
| tD-SU | Data setup time | 100 | |||
| tD-HD | Data hold time | 0 | 900 | ||
| tSCL-R | Rise time of SCL signal | 20 + 0.1 CB | 300 | ||
| tSCL-F | Fall time of SCL signal | 20 + 0.1 CB | 300 | ||
| tSDA-R | Rise time of SDA signal | 20 + 0.1 CB | 300 | ||
| tSDA-F | Fall time of SDA signal | 20 + 0.1 CB | 300 | ||
| tP-SU | Setup time for STOP condition | 0.6 | |||
| tGW | Allowable glitch width | 50 | |||
| CB | Capacitive load for SDA and SCL line | 100 | |||
| VNH | Noise margin at High level for each connected device (including hysteresis) | 0.2 × VDD | |||
| VNL | Noise margin at Low level for each connected device (including hysteresis) | 0.1 × VDD | |||
| VHYS | Hysteresis of Schmitt-trigger input | 0.05 × VDD | |||