亚洲国产无线乱码在线观看,被老板抱进卧室狂躁在线播放视频 ,国产人妖在线另类专区

SBFS036B May 2015 – August 2015 PCM2704C , PCM2705C , PCM2706C

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DB|28
- MPDS510A

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range unless otherwise noted. ⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_BUS	–0.3	6.5	V
Supply voltage	V_CCP, V_CCL, V_CCR, V_DD	–0.3	4	V
Supply voltage differences	V_CCP, V_CCL, V_CCR, V_DD		±0.1	V
Ground voltage differences	PGND, AGNDL, AGNDR, DGND, ZGND		±0.1	V
Digital input voltage	HOST	–0.3	6.5	V
Digital input voltage	D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT, PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3	–0.3	(V_DD + 0.3) < 4	V
Analog input voltage	V_COM	–0.3	(V_CCP + 0.3) < 4	V
	V_OUTR	–0.3	(V_CCR + 0.3) < 4	V
	V_OUTL	–0.3	(V_CCL + 0.3) < 4	V
Input current (any pins except supplies)		±10		mA
Ambient temperature under bias		–40	125	°C
Junction temperature			150	°C
Package temperature (IR reflow, peak)			260	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			MAX	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±3000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range.

		MIN	NOM	MAX	UNIT
Supply voltage	V_BUS	4.35	5	5.25	V
Supply voltage	V_CCP, V_CCL, V_CCR, V_DD	3	3.3	3.6	V
Digital input logic level		TTL-compatible
Digital input clock frequency		11.994	12	12.006	MHz
Analog output load resistance		16	32		Ω
Analog output load capacitance				100	pF
Digital output load capacitance				20	pF
Operating free-air temperature, T_A		–25		85	°C

7.4 Thermal Information: PCM2704C, PCM2705C

THERMAL METRIC⁽¹⁾		PCM2704C, PCM2705C	UNIT
		DB (SSOP)
		28 PINS
R_θJA	Junction-to-ambient thermal resistance	68.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	27.2	°C/W
R_θJB	Junction-to-board thermal resistance	29.5	°C/W
ψ_JT	Junction-to-top characterization parameter	2.7	°C/W
ψ_JB	Junction-to-board characterization parameter	29.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Thermal Information: PCM2706C, PCM2707C

THERMAL METRIC⁽¹⁾		PCM2706C, PCM2707C	UNIT
		PJT (TQFP)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	68.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	27.2	°C/W
R_θJB	Junction-to-board thermal resistance	29.5	°C/W
ψ_JT	Junction-to-top characterization parameter	2.7	°C/W
ψ_JB	Junction-to-board characterization parameter	29.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.6 Electrical Characteristics: PCM2704CDB, PCM2705CDB, PCM2706CPJT, PCM2707CPJT

All specifications at T_A = 25°C, V_BUS = 5 V, ƒ_S = 44.1 kHz, ƒ_IN = 1 kHz, and 16-bit data (unless otherwise noted). For the Host interface, apply USB revision 1.1, full-speed. For audio data format, use USB isochronous data format.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT LOGIC
V_IH	Input logic high level			2		3.3	V_DC
V_IH	Input logic high level⁽¹⁾			2		5.5	V_DC
V_IL	Input logic low level			–0.3		0.8	V_DC
V_IL	Input logic low level⁽¹⁾			–0.3		0.8	V_DC
I_IH	Input logic high current⁽²⁾		V_IN = 3.3 V			±10	μA
I_IH	Input logic high current		V_IN = 3.3 V		65	100	μA
I_IL	Input logic low current⁽²⁾		V_IN = 0 V			±10	μA
I_IL	Input logic low current		V_IN = 0 V			±10	μA
OUTPUT LOGIC
V_OH	Output logic high level⁽³⁾		I_OH = –2 mA	2.8			V_DC
V_OH	Output logic high level		I_OH = –2 mA	2.4			V_DC
V_OL	Output logic low level⁽³⁾		I_OL = 2 mA			0.3	V_DC
V_OL	Output logic low level		I_OL = 2 mA			0.4	V_DC
CLOCK FREQUENCY
	Input clock frequency, XTI			11.994	12	12.006	MHz
ƒ_S	Sampling frequency				32 44.1 48		kHz
DAC CHARACTERISTICS
	Resolution				16		bits
	Audio data channel				1, 2		channel
DC ACCURACY
	Gain mismatch, channel-to-channel				±2	±8	% of FSR
	Gain error				±2	±8	% of FSR
	Bipolar zero error				±3	±6	% of FSR
DYNAMIC PERFORMANCE ⁽⁴⁾
THD + N	Total harmonic distortion + noise	Line ⁽⁵⁾	R_L > 10 kΩ, self-powered, V_OUT = 0 dB		0.006%	0.01%
		Line ⁽⁵⁾	R_L > 10 kΩ, bus-powered, V_OUT = 0 dB		0.012%	0.02%
		Headphone	R_L = 32 Ω, self- or bus-powered, V_OUT = 0 dB		0.025%
THD + N	Total harmonic distortion + noise		V_OUT = –60 dB		2%
	Dynamic range		EIAJ, A-weighted	90	98		dB
SNR	Signal-to-noise ratio		EIAJ, A-weighted	90	98		dB
	Channel separation			60	70		dB
ANALOG OUTPUT
	Output voltage				0.55 V_CCL 0.55 V_CCR		V_PP
	Center voltage				0.5 V_CCP		V
	Load impedance	Line	AC-coupling	10			kΩ
	Load impedance	Headphone	AC-coupling	16	32		Ω
	LPF frequency response		–3 dB		140		kHz
	LPF frequency response		ƒ = 20 kHz		–0.1		dB
DIGITAL FILTER PERFORMANCE
	Passband					0.454 ƒ_S	Hz
	Stop band			0.546 ƒ_S			Hz
	Passband ripple					±0.04	dB
	Stop band attenuation			–50			dB
	Delay time				20 / ƒ_S		s
POWER SUPPLY REQUIREMENTS
	Voltage range	V_BUS	Bus-powered	4.35	5	5.25	V_DC
	Voltage range	V_CCP, V_CCL, V_CCR, V_DD	Self-powered	3	3.3	3.6	V_DC
	Supply current	Line	DAC operation		23	30	mA
		Headphone	DAC operation (R_L = 32 Ω)		35	46	mA
		Line/headphone	Suspend mode ⁽⁶⁾		150	190	μA
	Power dissipation (self-powered)	Line	DAC operation		76	108	mW
		Headphone	DAC operation (R_L = 32 Ω)		116	166	mW
		Line/headphone	Suspend mode ⁽⁶⁾		495	684	μW
	Power dissipation (bus-powered)	Line	DAC operation		115	158	mW
		Headphone	DAC operation (R_L = 32 Ω)		175	242	mW
		Line/headphone	Suspend mode ⁽⁶⁾		750	998	μW
	Internal power-supply voltage ⁽⁷⁾	V_CCP, V_CCL, V_CCR, V_DD	Bus-powered	3.2	3.35	3.5	V_DC
TEMPERATURE RANGE
	Operating temperature			–25		85	°C

(1) HOST pin.

(2) D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI pins.

(3) FUNC0, FUNC1, and FUNC2 pins.

(4) ƒ_IN = 1 kHz, using the System Two Cascade™ audio measurement system by Audio Precision® in RMS mode with a 20-kHz low-pass filter (LPF) and 400-Hz high-pass filter (HPF).

(5) THD + N performance varies slightly, depending on the effective output load, including dummy load R7 and R8 in Figure 35.

(6) In USB suspended state

(7) V_DD, V_CCP, V_CCL, V_CCR pins. These pins work as output pins of internal power supply for bus-powered operation.

7.7 Audio Interface Timing Characteristics

Load capacitance of LRCK, BCK, and DOUT is 20 pF. For timing diagrams, see Figure 1 and Figure 2.

		MIN	MAX	UNIT
t_(BCY)	BCK pulse cycle time	300		ns
t_(BCH)	BCK pulse duration, high	100		ns
t_(BCL)	BCK pulse duration, low	100		ns
t_(BL)	LRCK delay time from BCK falling edge	–20	40	ns
t_(BD)	DOUT delay time from BCK falling edge	–20	40	ns
t_(LD)	DOUT delay time from LRCK edge	–20	40	ns
t_(DS)	DIN setup time	20		ns
t_(DH)	DIN hold time	20		ns

7.8 Audio Clock Timing Characteristics

Load capacitance is 20 pF. For timing diagrams, see Figure 3.

		MIN	MAX	UNIT
t_(SLL), t_(SLH)	LRCK delay time from SYSCK rising edge	–5	10	ns
t_(SBL), t_(SBH)	BCK delay time from SYSCK rising edge	–5	10	ns

7.9 External ROM Read Interface Timing Characteristics

For timing diagrams, see Figure 4.

		MIN	MAX	UNIT
ƒ_(CK)	CK clock frequency		100	kHz
t_(BUF)	Bus free time between a STOP and a START condition	4.7		μs
t_(LOW)	Low period of the CK clock	4.7		μs
t_(HI)	High period of the CK clock	4		μs
t_(RS-SU)	Setup time for START/repeated START condition	4.7		μs
t_(S-HD) t_(RS-HD)	Hold time for START/repeated START condition	4		μs
t_(D-SU)	Data setup time	250		ns
t_(D-HD)	Data hold time	0	900	ns
t_(CK-R)	Rise time of CK signal	20 + 0.1 C_B	1000	ns
t_(CK-F)	Fall time of CK signal	20 + 0.1 C_B	1000	ns
t_(DT-R)	Rise time of DT signal	20 + 0.1 C_B	1000	ns
t_(DT-F)	Fall time of DT signal	20 + 0.1 C_B	1000	ns
t_(P-SU)	Setup time for STOP condition	4		μs
C_B	Capacitive load for DT and CK lines		400	pF
V_NH	Noise margin at high level for each connected device (including hysteresis)	0.2 V_DD		V

7.10 SPI Timing Characteristics

For timing diagrams, see Figure 5.

		MIN	UNIT
t_(MCY)	MC pulse cycle time	100	ns
t_(MCL)	MC low-level time	50	ns
t_(MCH)	MC high-level time	50	ns
t_(MHH)	MS high-level time	100	ns
t_(MLS)	MS falling edge to MC rising edge	20	ns
t_(MLH)	MS hold time	20	ns
t_(MDH)	MD hold time	15	ns
t_(MDS)	MD setup time	20	ns