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ZHCSPD8A April 2022 – September 2022 PCM1820-Q1 , PCM1821-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RTE|20
- MPQF596

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7.4 Electrical Characteristics

at T_A = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, f_IN = 1-kHz sinusoidal signal, f_S = 48 kHz, 32-bit audio data, BCLK = 256 × f_S, TDM slave mode (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ADC CONFIGURATION
	AC input impedance (PCM1820)	Input pins INxP or INxM			2.5		kΩ
	AC input impedance (PCM1821)	Input pins INxP or INxM			10		kΩ
PCM1820: ADC PERFORMANCE FOR LINE, MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
	Differential input full-scale AC signal voltage	AC-coupled input			2		V_RMS
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾	IN1 differential input selected and AC signal shorted to ground, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB)		115	122		dB
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾	IN1 differential input selected and AC signal shorted to ground, DRE disabled		106	112		dB
DR	Dynamic range, A-weighted⁽²⁾	IN1 differential input selected and –60-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB)			123		dB
DR	Dynamic range, A-weighted⁽²⁾	IN1 differential input selected and –60-dB full-scale AC signal input, DRE disabled			113		dB
THD+N	Total harmonic distortion⁽²⁾⁽³⁾	IN1 differential input selected and –1-dB full-scale AC signal input, DRE enabled (DRE_LVL = –36 dB, DRE_MAXGAIN = 24 dB)			–95	–80	dB
THD+N	Total harmonic distortion⁽²⁾⁽³⁾	IN1 differential input selected and –1-dB full-scale AC signal input, DRE disabled			–95		dB
PCM1821: ADC PERFORMANCE FOR LINE, MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
	Differential input full-scale AC signal voltage	AC-coupled input			2		V_RMS
SNR	Signal-to-noise ratio, A-weighted⁽¹⁾⁽²⁾	IN1 differential input selected and AC signal shorted to ground		100	106		dB
DR	Dynamic range, A-weighted⁽¹⁾⁽²⁾	IN1 differential input selected and –60-dB full-scale AC signal input			106		dB
THD+N	Total harmonic distortion⁽²⁾⁽³⁾	IN1 differential input selected and –1-dB full-scale AC signal input			–95		dB
ADC OTHER PARAMETERS
	Output data sample rate			7.35		192	kHz
	Output data sample word length					32	Bits
	Interchannel isolation	–1-dB full-scale AC-signal input to non measurement channel			–124		dB
	Interchannel gain mismatch	–6-dB full-scale AC-signal input			0.1		dB
	Gain drift⁽⁴⁾	Across temperature range -40°C to 125°C			50		ppm/°C
	Interchannel phase mismatch	1-kHz sinusoidal signal			0.02		Degrees
	Phase drift⁽⁵⁾	1-kHz sinusoidal signal, across temperature range -40°C to 125°C			0.0005		Degrees/°C
PSRR	Power-supply rejection ratio	100-mV_PP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain			102		dB
PCM1820: CMRR	Common-mode rejection ratio	Differential microphone input selected, 100-mV_PP, 1-kHz signal on both pins and measure level at output			45		dB
PCM1821: CMRR	Common-mode rejection ratio	Differential microphone input selected, 100-mV_PP, 1-kHz signal on both pins and measure level at output			60		dB
DIGITAL I/O
V_IL	Low-level digital input logic voltage threshold	All digital pins except FMT0, IOVDD 1.8-V operation		–0.3		0.30 × IOVDD	V
		All digital pins except FMT0, IOVDD 3.3-V operation		–0.3		0.8	V
		FMT0 Pin		–0.3		0.8	V
V_IH	High-level digital input logic voltage threshold	All digital pins except FMT0, IOVDD 1.8-V operation		0.7 × IOVDD		IOVDD + 0.3	V
		All digital pins except FMT0, IOVDD 3.3-V operation		2.1		IOVDD + 0.3	V
		FMT0 Pin		2.1		AVDD + 0.3	V
V_OL	Low-level digital output voltage	All digital pins, I_OL = –2 mA, IOVDD 1.8-V operation				0.45	V
V_OL	Low-level digital output voltage	All digital pins, I_OL = –2 mA, IOVDD 3.3-V operation				0.4	V
V_OH	High-level digital output voltage	All digital pins, I_OH = 2 mA, IOVDD 1.8-V operation		IOVDD – 0.45			V
V_OH	High-level digital output voltage	All digital pins, I_OH = 2 mA, IOVDD 3.3-V operation		2.4			V
I_IH	Input logic-high leakage for digital inputs	All digital pins except FMT0, input = IOVDD		–5	0.1	5	μA
I_IL	Input logic-low leakage for digital inputs	All digital pins except FMT0, input = 0 V		–5	0.1	5	μA
I_IH	Input logic-high leakage for digital inputs	FMT0 Pin, input = AVDD	All digital pins, input = AVDD	–5	0.1	5	μA
I_IL	Input logic-low leakage for digital inputs	FMT0 Pin , input = 0 V	All digital pins, input = 0 V	–5	0.1	5	μA
C_IN	Input capacitance for digital inputs	All digital pins			5		pF
R_PD	Pulldown resistance for digital I/O pins when asserted on				20		kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
I_AVDD	Current consumption with all Clocks disabled	AVDD = 3.3 V, internal AREG			0.5		mA
I_IOVDD		All external clocks stopped, IOVDD = 3.3 V			0.5		μA
I_IOVDD		All external clocks stopped, IOVDD = 1.8 V			0.3		μA
I_AVDD	Current consumption with ADC 2-channel operating at f_S 16-kHz, BCLK = 256 × f_S and DRE disabled	AVDD = 3.3 V, internal AREG			11.9		mA
I_IOVDD		IOVDD = 3.3 V			0.05
I_IOVDD		IOVDD = 1.8 V			0.02
I_AVDD	Current consumption with ADC 2-channel operating at f_S 48-kHz, BCLK = 256 × f_S and DRE disabled	AVDD = 3.3 V, internal AREG			12.9		mA
I_IOVDD		IOVDD = 3.3 V			0.1
I_IOVDD		IOVDD = 1.8 V			0.05
I_AVDD	Current consumption with ADC 2-channel operating at f_S 48-kHz, BCLK = 256 × f_S and DRE enabled	AVDD = 3.3 V, internal AREG			14		mA
I_IOVDD		IOVDD = 3.3 V			0.1
I_IOVDD		IOVDD = 1.8 V			0.05

(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2) All performance measurements done with a 20-kHz, low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3) For best distortion performance, use input AC-coupling capacitors with a low-voltage-coefficient.

(4) Gain drift =gain_variation(in temperature range)/ typical gain value(gain at room temperature) / temperature range × 10⁶ measured with gain in linear scale.

(5) Phase drift =phase_deviation(in temperature range)/ (temperature range).