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SLES254D April 2010 – July 2015 PCM1753-Q1 , PCM1754-Q1

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DBQ|16
- MSOI004H

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	V_CC	–0.3	6.5	V
Ground voltage differences	AGND, DGND	–0.1	0.1	V
Input voltage		–0.3	6.5	V
Input current (any pins except supplies)		–10	10	mA
Ambient temperature under bias		–40	105	°C
Junction temperature			150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100–002⁽¹⁾		±2000	V
		Charged device model (CDM), per AEC Q100–011	Corner pins (1, 8, 9, and 16)	±750
		Charged device model (CDM), per AEC Q100–011	Other pins	±500

(1) AEC Q100–002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS–001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Voltage range	4.5	5	5.5	VDC

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		PCM175x-Q1	UNIT
		DBQ (SSOP)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	111.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	57.4	°C/W
R_θJB	Junction-to-board thermal resistance	55.1	°C/W
ψ_JT	Junction-to-top characterization parameter	13.5	°C/W
ψ_JB	Junction-to-board characterization parameter	54.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

All specifications at T_A = 25°C, V_CC = 5 V, f_S = 44.1 kHz, system clock = 384 f_S, and 24-bit data (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution			24		Bits
DATA FORMAT
f_S	Sampling frequency		5		200	kHz
	System clock frequency⁽³⁾			128 f_S 192 f_S 256 f_S 384 f_S 512 f_S 768 f_S 1152 f_S		kHz
DIGITAL INPUT/OUTPUT
	Logic family		TTL compatible
V_IH	Input logic level, high		2			VDC
V_IL	Input logic level, low				0.8	VDC
I_IH	Input logic current, high (SCK, BCK, DATA, and LRCK pins)	V_IN = V_CC			10	µA
I_IL	Input logic current, low (SCK, BCK, DATA, and LRCK pins)	V_IN = 0 V			–10	µA
I_IH	Input logic current, high (TEST, DEMP, MUTE, and FMT pins)	V_IN = V_CC		65	100	µA
I_IL	Input logic current, low (TEST, DEMP, MUTE, and FMT pins)	V_IN = 0 V			–10	µA
V_OH	Output logic level, high (ZEROA pin)	I_OH = –1 mA	2.4			VDC
V_OL	Output logic level, low (ZEROA pin)	I_OL = 1 mA			0.4	VDC
DYNAMIC PERFORMANCE⁽¹⁾⁽²⁾
	THD+N at VOUT = 0 dB	f_S = 44.1 kHz		0.00%	0.01%
		f_S = 96 kHz		0.00%
		f_S = 192 kHz		0.00%
	THD+N at VOUT = -60 dB	f_S = 44.1 kHz		0.65%
		f_S = 96 kHz		0.80%
		f_S = 192 kHz		0.95%
	Dynamic range	EIAJ, A-weighted, f_S = 44.1 kHz	100	106		dB
		A-weighted, f_S = 96 kHz		104
		A-weighted, f_S = 192 kHz		102
	Signal-to-noise ratio	EIAJ, A-weighted, f_S = 44.1 kHz	100	106		dB
		A-weighted, f_S = 96 kHz		104
		A-weighted, f_S = 192 kHz		102
	Channel separation	f_S = 44.1 kHz	97	103		dB
		f_S = 96 kHz		101
		f_S = 192 kHz		100
	Level linearity error	VOUT = -90 dB		±0.5		dB
DC ACCURACY
	Gain error			±1	±6	% of FSR
	Gain mismatch, channel-to-channel			±1	±3	% of FSR
	Bipolar zero error	VOUT = 0.5 V_CC at BPZ		±30	±60	mV
ANALOG OUTPUT
	Output voltage	Full scale (0 dB)	80% of V_CC			V_PP
	Center voltage		50% of V_CC			VDC
	Load impedance	AC-coupled load	5			kΩ
DIGITAL FILTER PERFORMANCE
FILTER CHARACTERISTICS (SHARP ROLLOFF)
	Pass band	±0.04 dB			0.454 f_S
	Stop band		0.546 fs
	Pass-band ripple				±0.04	dB
	Stop-band attenuation	Stop band = 0.546 f_S	–50			dB
ANALOG FILTER PERFORMANCE
	Frequency response	At 20 kHz		–0.03		dB
	Frequency response	At 44 kHz		–0.20		dB
POWER SUPPLY REQUIREMENTS⁽²⁾
V_CC	Voltage range		4.5	5	5.5	VDC
I_CC	Supply current	f_S = 44.1 kHz		16	21	mA
		f_S = 96 kHz		25
		f_S = 192 kHz		30
	Power dissipation	f_S = 44.1 kHz		80	105	mW
		f_S = 96 kHz		125
		f_S = 192 kHz		150
TEMPERATURE RANGE
	Operation temperature		–40		105	°C
R_θJA	Thermal resistance	16-pin SSOP		115		°C/W

(1) Analog performance specifications are measured using the System Two™ Cascade audio measurement system by Audio Precision™ in the averaging mode.

(2) Conditions in 192-kHz operation are system clock = 128 f_S and oversampling rate = 64 f_S of register 18.

(3) System Clock: 128 f_S, 192 f_S, 256 f_S, 384 f_S, 512 f_S, 768 f_S, 1152 f_S with auto detect.

7.6 System Clock Input Timing

For more information, see the System Clock Input section.

			MIN	NOM	UNIT
t_(SCKH)	System clock pulse duration, high	See Figure 20.	7		ns
t_(SCKL)	System clock pulse duration, low		7		ns
t_(SCY)	System clock pulse cycle time			See ⁽¹⁾	ns

(1) 1/128 f_S, 1/256 f_S, 1/384 f_S, 1/512 f_S, 1/768 f_S, or 1/1152 f_S

7.7 Audio Interface Timing

For more information, see the Audio Data Formats and Timing section.

			MIN	UNIT
t_(BCY)	BCK pulse cycle time	See Figure 22.	1/(32 f_S) 1/(48 f_S) 1/(64 f_S)⁽¹⁾	ns
t_(BCH)	BCK high–level time		35	ns
t_(BCL)	BCK low–level time		35	ns
t_(BL)	BCK rising edge to LRCK edge		10	ns
t_(LB)	LRCK falling edge to BCK rising edge		10	ns
t_(DS)	DATA setup time		10	ns
t_(DH)	DATA hold time		10	ns

(1) f_S is the sampling frequency (such as, 44.1 kHz, 48 kHz, 96 kHz, and so on).

7.8 Control Interface Timing Requirements

These timing parameters are critical for proper control port operation.

			MIN	UNIT
t_(MCY)	MC pulse cycle time	See Figure 1.	100	ns
t_(MCL)	MC low-level time		50	ns
t_(MCH)	MC high-level time		50	ns
t_(MCH)	ML high-level time		See ⁽²⁾	ns
t_(MLS)	ML falling edge to MC rising edge		20	ns
t_(MLH)	ML hold time⁽¹⁾		20	ns
t_(MDH)	MD hold time		15	ns
t_(MDS)	MD setup time		20	ns