ZHCSK28E April 2003 – July 2019 PCM1753 , PCM1754 , PCM1755
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1
Mode Control Registers (PCM1753/55)
- 8.6.1.1 User-Programmable Mode Controls
- 8.6.1.2
Register Definitions
- 8.6.1.2.1 ATx[7:0]: Digital Attenuation Level Setting
- 8.6.1.2.2 MUTx: Soft Mute Control
- 8.6.1.2.3 OVER: Oversampling Rate Control
- 8.6.1.2.4 SRST: Reset
- 8.6.1.2.5 DACx: DAC Operation Control
- 8.6.1.2.6 DM12: Digital De-Emphasis Function Control
- 8.6.1.2.7 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function
- 8.6.1.2.8 FMT[2:0]: Audio Interface Data Format
- 8.6.1.2.9 FLT: Digital Filter Rolloff Control
- 8.6.1.2.10 DREV: Output Phase Select
- 8.6.1.2.11 ZREV: Zero Flag Polarity Select
- 8.6.1.2.12 AZRO: Zero Flag Function Select
- 8.6.1
Mode Control Registers (PCM1753/55)
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DBQ|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
8.3.1.2 Power-On Reset Functions
The PCM175x devices include a power-on reset function. Figure 21 shows the operation of this function. With the system clock active and VCC > 3 V (typical, 2.2 V to 3.7 V), the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VCC > 3 V (typical, 2.2 V to 3.7 V).
During the reset period (1024 system clocks), the analog output is forced to the bipolar zero level, or VCC/2. After the reset period, an internal register is initialized in the next 1/fS period and if SCK, BCK, and LRCK are provided continuously, the PCM175x devices provide proper analog output with unit group delay against the input data.
Figure 21. Power-On Reset Timing