ZHCSSV1 august 2023 MCF8316C-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Output Stage
- 7.3.2 Device Interface
- 7.3.3 Step-Down Mixed-Mode Buck Regulator
- 7.3.4 AVDD Linear Voltage Regulator
- 7.3.5 Charge Pump
- 7.3.6 Slew Rate Control
- 7.3.7 Cross Conduction (Dead Time)
- 7.3.8 Motor Control Input Sources
- 7.3.9 Starting the Motor Under Different Initial Conditions
- 7.3.10 Motor Start Sequence (MSS)
- 7.3.11 Closed Loop Operation
- 7.3.12 Motor Parameters
- 7.3.13 Motor Parameter Extraction Tool (MPET)
- 7.3.14 Anti-Voltage Surge (AVS)
- 7.3.15 Active Braking
- 7.3.16 Output PWM Switching Frequency
- 7.3.17 PWM Modulation Schemes
- 7.3.18 Dead Time Compensation
- 7.3.19 Motor Stop Options
- 7.3.20 FG Configuration
- 7.3.21 DC Bus Current Limit
- 7.3.22
Protections
- 7.3.22.1 VM Supply Undervoltage Lockout
- 7.3.22.2 AVDD Undervoltage Lockout (AVDD_UV)
- 7.3.22.3 BUCK Under Voltage Lockout (BUCK_UV)
- 7.3.22.4 VCP Charge Pump Undervoltage Lockout (CPUV)
- 7.3.22.5 Overvoltage Protection (OVP)
- 7.3.22.6 Overcurrent Protection (OCP)
- 7.3.22.7 Buck Overcurrent Protection
- 7.3.22.8 Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
- 7.3.22.9 Lock Detection Current Limit (LOCK_ILIMIT)
- 7.3.22.10 FET Thermal Warning (OTW)
- 7.3.22.11 FET Thermal Shutdown (TSD_FET)
- 7.3.22.12 Motor Lock (MTR_LCK)
- 7.3.22.13 Motor Lock Detection
- 7.3.22.14 MPET Faults
- 7.3.22.15 IPD Faults
- 7.4 Device Functional Modes
- 7.5 External Interface
- 7.6 EEPROM access and I2C interface
- 7.7 EEPROM (Non-Volatile) Register Map
- 7.8 RAM (Volatile) Register Map
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGF|40
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGF|40
訂購信息
7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
When an OCP event happens in this mode, all the FETs are disabled and the nFAULT pin is driven low. The DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b in the fault status registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after the tRETRY (TRETRY) time elapses. The DRIVER_FAULT bit is reset to 0b after the tRETRY period expires. The OCP and corresponding FET's OCP bits are set to 1b until cleared through the CLR_FLT bit.
Figure 7-52 Overcurrent Protection - Automatic Retry Mode