ZHCSS74B january 2015 – june 2023 LV2862
PRODUCTION DATA
Figure 5-1 SOT (DDC)6
PinsTop View| PIN | DESCRIPTION | |
|---|---|---|
| NAME | NO. | |
| CB | 1 | Switch FET gate bias voltage. Connect Cboot cap between CB and SW. |
| GND | 2 | Ground connection |
| FB | 3 | Set feedback voltage divider ratio with VOUT = VFB (1 + (R1 / R2)) |
| SHDN | 4 | Enable and disable input (high voltage tolerant). Internal pullup current source. Pull below 1.25 V to disable. Float to enable. Establish the input undervoltage lockout with a two-resistor divider. |
| VIN | 5 | Power input voltage pin. Input for internal supply and drain node input for internal high-side MOSFET. |
| SW | 6 | Switch node. Connect to inductor, diode, and Cboot cap. |