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ZHCSHY8 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

PRODUCTION DATA.

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RNF|26

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics

–40°C ≤ T_J ≤ +140°C, C_POL = 22 µF/phase, specified V_VANA, V_{VIN_Bx} , V_NRST, V_{VOUT_Bx}, and I_OUT range, unless otherwise noted. Typical values are at T_J = 25°C, V_VANA = V_{VIN_Bx} = 3.7 V, and V_OUT = 1 V, unless otherwise noted⁽¹⁾⁽²⁾.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
EXTERNAL COMPONENTS
C_IN	Input filtering capacitance		Connected from VIN_Bx to PGND_Bx	1.9	10		µF
C_OUT	Output filtering capacitance per phase, local			10	22		µF
C_POL	Optional point-of-load (POL) capacitance per phase				22		µF
C_OUT-TOTAL	Total output capacitance⁽³⁾ (local and POL)	4-phase output	Output voltage slew-rate ≤ 1.9 mV/µs			2000	µF
		3-phase output	Output voltage slew-rate ≤ 1.9 mV/µs			1500
		2-phase output	Output voltage slew-rate ≤ 1.9 mV/µs			1000
		1-phase output	Output voltage slew-rate ≤ 1.9 mV/µs			500
ESR_C	ESR of the input and output capacitor		1 MHz ≤ f ≤ 10 MHz		2	10	mΩ
L	Inductance of the inductor				0.47		µH
L	Inductance of the inductor			–30%		30%
DCR_L	Inductor DCR				25		mΩ
BUCK REGULATOR
V_{VIN_Bx}	Input voltage range			2.8	3.7	5.5	V
V_{VOUT_Bx}	Programmable output voltage range			0.6		3.36	V
	Output voltage step size		0.6 V ≤ V_VOUT< 0.73 V		10		mV
			0.73 V ≤ V_VOUT < 1.4 V		5
			1.4 V ≤ V_VOUT ≤ 3.36 V		20
I_OUT	Output current⁽⁴⁾	4-phase output	V_IN ≥ 3 V			16	A
		4-phase output	2.8 V ≤ V_IN < 3 V			12
		3-phase output	V_IN ≥ 3 V			12
		3-phase output	2.8 V ≤ V_IN < 3 V			9
		2-phase output	V_IN ≥ 3 V			8
		2-phase output	2.8 V ≤ V_IN < 3 V			6
		1-phase output	V_IN ≥ 3 V			4
		1-phase output	2.8 V ≤ V_IN < 3 V			3
	Input and output voltage difference Minimum voltage between VIN_x and V_OUT to fulfill the electrical characteristics			0.5			V
V_{VOUT_DC}	DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, and temperature		V_OUT< 1 V, PWM mode	–20		20	mV
			V_OUT ≥ 1 V, PWM mode	–2%		2%
			V_OUT< 1 V, PFM mode	–20		40	mV
			V_OUT ≥ 1 V, PFM mode	–2%		2% + 20 mV
	Ripple voltage	4-phase output	PWM mode, ESR_C < 2 mΩ, L = 0.47 µH		3		mV_p-p
		4-phase output	PFM mode, L = 0.47 µH		4
		3-phase output	PWM mode, ESR_C < 2 mΩ, L = 0.47 µH		4
		3-phase output	PFM mode, L = 0.47 µH		5
		2-phase output	PWM mode, ESR_C < 2 mΩ, L = 0.47 µH		6
		2-phase output	PFM mode, L = 0.47 µH		7
		1-phase output,	PWM mode, ESR_C < 2 mΩ, L = 0.47 µH		8
		1-phase output,	PFM mode, L = 0.47 µH		14
DC_LNR	DC line regulation		I_OUT = I_OUT(max)		0.1		%/V
DC_LDR	DC load regulation in PWM mode		V_OUT = 1 V, 0 A ≤ I_OUT ≤ I_OUT(max)		0.8%
T_LDSR	Transient load step response	4-phase output	0 A ≤ I_OUT ≤ 8 A, t_r = t_f = 10 µs, PWM mode, C_OUT = 22 µF/phase, L = 0.47 µH, C_POL = 22 µF/phase	–3%		3%	mV
		4-phase output	0.1 A ≤ I_OUT ≤ 8 A, t_r = t_f = 1 µs, PWM mode, C_OUT = 22 µF/phase, L = 0.47 µH, C_POL = 22 µF/phase		±40
		3-phase output	0 A ≤ I_OUT ≤ 6 A, t_r = t_f = 10 µs, PWM mode, C_OUT = 22 µF/phase, L = 0.47 µH, C_POL = 22 µF/phase	–3%		3%
		3-phase output	0.1 A ≤ I_OUT ≤ 6 A, t_r = t_f = 1 µs, PWM mode, C_OUT = 22 µF/phase, L = 0.47 µH, C_POL = 22 µF/phase		±40
		2-phase output	0 A ≤ I_OUT ≤ 4 A, t_r = t_f = 10 µs, PWM mode, C_OUT = 22 µF/phase, L = 0.47 µH, C_POL = 22 µF/phase	–3%		3%
		2-phase output	0.1 A ≤ I_OUT ≤ 4 A, t_r = t_f = 1 µs, PWM mode, C_OUT = 22 µF/phase, L = 0.47 µH, C_POL = 22 µF/phase		±40
		1-phase output	0 A ≤ I_OUT ≤ 2 A, t_r = t_f = 10 µs, PWM mode, C_OUT = 22 µF, L = 0.47 µH, C_POL = 22 µF	–3%		3%
		1-phase output	0.1 A ≤ I_OUT ≤ 2 A, t_r = t_f = 1 µs, PWM mode, C_OUT = 22 µF, L = 0.47 µH, C_POL = 22 µF		±40
T_LNSR	Transient line response		V_{VIN_Bx} stepping 3 V ↔ 3.5 V, t_r = t_f = 10 µs, I_OUT = I_OUT(max)		±5		mV
I_{LIM FWD}	Forward current limit for each phase (peak for each switching cycle)		Programmable range	1.5		5	A
			Step size		0.5		A
			Accuracy, V_{VIN_Bx} ≥ 3 V, ILIM ≥ 3 A	–5%	7.5%	20%
			Accuracy, 2.8 V ≤ V_{VIN_Bx}< 3 V, I_LIM ≥ 3. A	–20%	7.5%	20%
I_{LIM NEG}	Negative current limit per phase (peak for each switching cycle)			1.6	2	2.4	A
R_{DS(ON) HS FET}	On-resistance, high-side FET		Each phase, between VIN_Bx and SW_Bx pins, I = 1 A		29	65	mΩ
R_{DS(ON) LS FET}	On-resistance, low-side FET		Each phase, between SW_Bx and PGND_Bx pins, I = 1 A		17	35	mΩ
f_SW	Switching frequency, PWM mode			1.8	2	2.2	MHz
	Current balancing for multiphase outputs		Current mismatch between phases, I_OUT> 1 A/phase			10%
	Start-up time (soft start)		From ENx to V_OUT = 0.35 V (slew-rate control begins), C_{OUT_TOTAL} = 44 µF/phase		200		µs
	Output voltage slew-rate⁽⁵⁾		SLEW_RATEx[2:0] = 2h, C_OUT-TOTAL ≤ 80 µF/phase	–15%	10	15%	mV/µs
			SLEW_RATEx[2:0] = 3h, C_OUT-TOTAL ≤ 130 µF/phase	–15%	7.5	15%
			SLEW_RATEx[2:0] = 4h, C_OUT-TOTAL ≤ 250 µF/phase	–15%	3.8	15%
			SLEW_RATEx[2:0] = 5h, C_OUT-TOTAL ≤ 500 µF/phase	–15%	1.9	15%
			SLEW_RATEx[2:0] = 6h, C_OUT-TOTAL ≤ 500 µF/phase	–15%	0.94	15%
			SLEW_RATEx[2:0] = 7h, C_OUT-TOTAL ≤ 500 µF/phase	–15%	0.47	15%
I_PFM-PWM	PFM-to-PWM current threshold⁽⁶⁾				600		mA
I_PWM-PFM	PWM-to-PFM current threshold⁽⁶⁾				200		mA
I_ADD	Phase adding level (multiphase rails)		From 1-phase to 2-phase		1		A
			From 2-phase to 3-phase		2
			From 3-phase to 4-phase		3
I_SHED	Phase shedding level (multiphase rails)		From 2-phase to 1-phase		0.7		A
			From 3-phase to 2-phase		1.5
			From 4-phase to 3-phase		2.4
	Output pulldown resistance		Regulator disabled	160	230	300	Ω
	Output voltage monitoring for PGOOD pin		Overvoltage monitoring (compared to DC output-voltage level, V_{VOUT_DC})	39	50	64	mV
			Undervoltage monitoring (compared to DC output-voltage level, V_{VOUT_DC})	–53	–40	–29	mV
			Debounce time during regulator enable PGOOD_SET_DELAY = 0h	4		10	µs
			Debounce time during regulator enable PGOOD_SET_DELAY = 1h	10	11	13	ms
			Deglitch time during operation and after voltage change	4		10	µs
	Power-good threshold for interrupt BUCKx_PG_INT, difference from final voltage		Rising ramp voltage, enable or voltage change	–20	–14	–8	mV
			Falling ramp voltage, voltage change	8	14	20	mV
	Power-good threshold for status bit BUCKx_PG_STAT		During operation, status signal is forced to 0h during voltage change	–20	–14	–8	mV
EXTERNAL CLOCK AND PLL
	Nominal frequency of the external input clock			1		24	MHz
	Nominal frequency step size of the external input clock				1		MHz
	Required accuracy from nominal frequency of the external input clock			–30%		10%
	Delay time for missing external clock detection					1.8	µs
	Delay and debounce time for external clock detection					20	µs
	Clock change delay (internal to external) delay from valid clock detection to use of external clock				600		µs
	Cycle-to-cycle PLL output clock jitter				300		ps, p-p
PROTECTION FUNCTIONS
	Thermal warning		Temperature rising, TDIE_WARN_LEVEL = 0h	115	125	135	°C
	Thermal warning		Temperature rising, TDIE_WARN_LEVEL = 1h	127	137	147	°C
	Thermal warning hysteresis				20		°C
	Thermal shutdown		Temperature rising	140	150	160	°C
	Thermal shutdown hysteresis				20		°C
VANA_OVP	VANA overvoltage		Voltage rising	5.6	5.8	6.1	V
VANA_OVP	VANA overvoltage		Voltage falling	5.45	5.73	5.96	V
	VANA overvoltage hysteresis			40			mV
VANA_UVLO	VANA undervoltage lockout		Voltage rising	2.51	2.63	2.75	V
VANA_UVLO	VANA undervoltage lockout		Voltage falling	2.5	2.6	2.7	V
LOAD CURRENT MEASUREMENT
	Current measurement range		Output current for maximum code			20.47	A
	Resolution		LSB		20		mA
	Measurement accuracy		I_OUT> 1 A		< 10%
	Measurement time		PFM mode (automatically changing to PWM mode for the measurement)		45		µs
	Measurement time		PWM mode		4		µs
CURRENT CONSUMPTION
	Shutdown current consumption		From VANA and VIN_Bx pins, NRST = 0 V, VANA = VIN_Bx = 3.7 V		1.4		µA
	Standby current consumption		From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, regulators disabled		6.7		µA
	Active current consumption in PFM mode		4-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, I_OUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled		77		µA
			3-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, I_OUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled		71
			2-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, I_OUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled		65
			1-phase enabled: From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, I_OUT = 0 mA, not switching, one regulator enabled, internal RC oscillator, PGOOD monitoring enabled		57
	Active current consumption during PWM operation		Each phase		17		mA
	PLL and clock detector current consumption		Additional current consumption when internal RC oscillator, clock detector and PLL are enabled		2		mA
DIGITAL INPUT SIGNALS: NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
V_IL	Input low level					0.4	V
V_IH	Input high level			1.2			V
V_HYS	Hysteresis of Schmitt trigger inputs			10	77	200	mV
	ENx pulldown resistance		ENx_PD = 1h		500		kΩ
	NRST pulldown resistance		Always present	650	1150	1700	kΩ
DIGITAL OUTPUT SIGNALS: nINT
V_OL	Output low level		I_SOURCE = 2 mA			0.4	V
R_P	External pullup resistor		To VIO supply		10		kΩ
DIGITAL OUTPUT SIGNALS: SDA
V_OL	Output low level		I_SOURCE = 10 mA			0.4	V
DIGITAL OUTPUT SIGNALS: PGOOD, GPIO1, GPIO2, GPIO3
V_OL	Output low level		I_SOURCE = 2 mA			0.4	V
V_OH	Output high level, configured to push-pull		I_SINK = 2 mA	V_VANA – 0.4		V_VANA	V
V_PU	Supply voltage for external pull-up resistor, configured to open-drain					V_VANA	V
R_PU	External pullup resistor, configured to open-drain				10		kΩ
ALL DIGITAL INPUTS
I_LEAK	Input current		All logic inputs over pin voltage range (except NRST)	−1		1	µA

(1) All voltage values are with respect to network ground.

(2) Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm.

(3) The output voltage slew-rate setting may limit the maximum output capacitance.

(4) The maximum output current can be limited by the forward current limit I_{LIM FWD} and by the junction temperature. The power dissipation inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown level if the board and ambient temperatures are high.

(5) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The actual set fixed slew rate value for specific part number is listed in corresponding TRM document.

(6) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and the inductor current level.