97热久久免费频精品99,国产亚洲国际精品福利

ZHCSDY3 May 2015 LMX2581E

PRODUCTION DATA.

封裝選項(xiàng)

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Vcc	Power supply voltage	–0.3	3.6	V
V_IN	Input voltage to pins other than Vcc pins	–0.3	(Vcc + 0.3)	V
T_L	Lead temperature (solder 4 sec.)		260	°C
T_J	Junction temperature		150	°C
V_OSCin	Voltage on OSCin (Pin29)	≤1.8 with Vcc Applied ≤1 with Vcc = 0		Vpp
Storage Temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
Vcc	Power Supply Voltage	3.15	3.3	3.45	V
T_J	Junction Temperature			125	°C
T_A	Ambient Temperature	-40		85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LMX2581E	UNIT
		DAP (WQFN)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance	30	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance
R_θJB	Junction-to-board thermal resistance
ψ_JT	Junction-to-top characterization parameter
ψ_JB	Junction-to-board characterization parameter
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

(3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ T_A ≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.)

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_CC	Entire chip supply current	One Output Enabled OUTx_PWR = 15			178		mA
I_CCCore	Supply current except for output buffers	Output Buffers and VCO Divider Disabled.			134		mA
I_CCRFout	Additive current for each output buffer	OUTx_PWR = 15			44		mA
I_CCVCO_DIV	Additive VCO divider current	VCO Divider Enabled			20		mA
I_CCPD	Power down current	Device Powered Down (CE Pin = LOW)			7		mA
OSCin REFERENCE INPUT
f_OSCin	OSCin frequency range	Doubler Enabled		5		250	MHz
f_OSCin	OSCin frequency range	Doubler Disabled		5		900	MHz
v_OSCin	OSCin input voltage	AC Coupled		0.4		1.7	Vpp
Spur_Foscin	Oscin spur	Foscin = 100 MHz, Offset = 100 MHz			-81		dBc
PLL
f_PD	Phase detector frequency					200	MHz
K_PD	Charge-pump gain	Gain = 1X			110		µA
		Gain = 2X			220
		...			...
		Gain = 31X			3410
PN_{PLL_1/f_Norm}	Normalized PLL 1/f noise ⁽¹⁾	Gain =31X Normalized to 1 GHz carrier and 10 kHz Offset			–120.8		dBc/Hz
PN_{PLL_FOM}	PLL figure of merit (Normalized Noise Floor) ⁽¹⁾	Gain =31X. Normalized to PLL1 and f_PD=1Hz			–229		dBc/Hz
f_RFin	External VCO input pin frequency	Internal VCOs Bypassed (OUTA_PD=OUTB_PD=1)		0.5		2.2	GHz
p_RFin	External VCO input pin power	Internal VCOs Bypassed (OUTA_PD=OUTB_PD=1)		0		+8	dBm
Spur_Fpd	Phase detector spurs ⁽²⁾	Fpd = 25 MHz			–85		dBc
Spur_Fpd	Phase detector spurs ⁽²⁾	Fpd = 100 MHz			–81		dBc
OUTPUTS
p_RFoutA+/- p_RFoutB+/-	Output power level⁽⁵⁾⁽⁵⁾	Inductor Pullup F_OUT = 2.7 GHz	OUTx_PWR=15		7.3		dBm
p_RFoutA+/- p_RFoutB+/-	Output power level⁽⁵⁾⁽⁵⁾	Inductor Pullup F_OUT = 2.7 GHz	OUTx_PWR=45		12		dBm
H2_RFoutX+/-	Second harmonic ⁽⁶⁾	F_OUT = 2.7 GHz	OUTx_PWR=15		–25		dBc
VCO
f_VCO		Before the VCO Divider	All VCO Cores Combined	1880		3800	MHz
K_VCO	VCO gain	Vtune = 1.3 Volts	Core 1		12 to 24		MHz/V
			Core 2		15 to 30
			Core 3		20 to 37
			Core 4		21 to 37
ΔT_CL	Allowable temperature drift ⁽³⁾	VCO not being re-calibrated	Fvco ≥2.5 GHz	–125		+125	°C
ΔT_CL	Allowable temperature drift ⁽³⁾	VCO not being re-calibrated	Fvco < 2.5 GHz	–100		+125	°C
t_VCOCal	VCO calibration time ⁽⁴⁾	f_OSCin = 100 MHz f_PD = 100 MHz Full Band Change 1880 — 3800 MHz	No Pre-programming		140		µs
t_VCOCal	VCO calibration time ⁽⁴⁾		With Pre-programming		10		µs
PN_VCO	VCO phase noise (OUTx_PWR =15)	f_VCO = 1.9 GHz Core 1	10 kHz Offset		–85.4		dBc/Hz
			100 kHz Offset		–114.5
			1 MHz Offset		–137.0
			10 MHz Offset		–154.2
			40 MHz Offset		–156.7
		f_VCO = 2.2 GHz Core 2	10 kHz Offset		–84.6		dBc/Hz
			100 kHz Offset		–114.1
			1 MHz Offset		–137.5
			10 MHz Offset		–154.5
			40 MHz Offset		–156.1
		f_VCO = 2.7 GHz Core 3	10 kHz Offset		–81.7		dBc/Hz
			100 kHz Offset		–112.2
			1 MHz Offset		–136.0
			10 MHz Offset		–153.1
			40 MHz Offset		–155.0
		f_VCO = 3.3 GHz Core 4	10 kHz Offset		–79.0		dBc/Hz
			100 kHz Offset		–108.6
			1 MHz Offset		–132.6
			10 MHz Offset		–152.0
			40 MHz Offset		–155.0
DIGITAL INTERFACE (DATA, CLK, LE, CE, MUXout, BUFEN, LD)
V_IH	High-level input voltage			1.4		Vcc	V
V_IL	Low level input voltage					0.4	V
I_IH	High-level input current	V_IH = 1.75 V		–5		5	µA
I_IL	Low-level input current	V_IL = 0 V		–5		5	µA
V_OH	High-level output voltage	I_OH = –500 µA		2			V
V_OL	Low-Level output voltage	I_OL = –500 µA			0	0.4	V

(1) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into 1/f and flat components. PLL_Flat = PLL_FOM + 20*log(Fvco/Fpd)+10*log(Fpd / 1Hz). PLL_1/f = PLL_1/f_Norm + 20*log(Fvco / 1GHz) - 10*log(Offset/10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10*log( 10^PLL_Flat/10) + 10^{PLL_1/f / 10} )

(2) The spurs at the offset of the phase detector frequency are dependent on many factors, such as he phase detector frequency.

(3) Continuous tuning range over temperature refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.

(4) VCO digital calibration time is the amount of time it takes for the VCO to find the correct frequency band when switching to a new frequency. After the correct frequency band is found , the remaining error is typically less than 1 MHz and then the PLL settles the rest of the error in an analog manner. Pre-programming refers to specifying a band that is close to the final (< 20 MHz), which greatly improves the VCO calibration time.

(5) The output power is dependent of the setup and is also programmable. Consult Application and Implementation for more information.

(6) The harmonics vary as a function of frequency, output termination, board layout, and output power setting.

7.6 Timing Requirements, MICROWIRE Timing

	See Figure 1	MIN	UNIT
t_ES	Clock-to-enable low time	35	ns
t_CS	Data-to-clock set up time	10	ns
t_CH	Data-to-clock hold time	10	ns
t_CWH	Clock pulse width high	25	ns
t_CWL	Clock pulse width low	25	ns
t_CES	Enable-to-clock setup time	10	ns
t_EWH	Enable pulse width high	10	ns