ZHCSXO2 December 2024 LMX1205
ADVANCE INFORMATION
| D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| R0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | POWERDOWN | 復(fù)位 |
| R1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LD_DIS | READBACK_CTRL | 0 | 1 | 1 |
| R2 | 0 | 0 | 0 | 0 | 0 | 0 | TEMPSENSE_EN | SYNC_EN | 1 | SYSREF_EN | 1 | LOGIC_EN | CH3_EN | CH2_EN | CH1_EN | CH0_EN |
| R3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | CLKIN_DLY | ||||||
| R4 | 0 | 0 | 0 | 0 | 0 | CLK0_DLY | CLK0_PWR | CLK0_EN | ||||||||
| R5 | 0 | 0 | 0 | 0 | 0 | CLK1_DLY | CLK1_PWR | CLK1_EN | ||||||||
| R6 | 0 | 0 | 0 | 0 | 0 | CLK2_DLY | CLK2_PWR | CLK2_EN | ||||||||
| R7 | 0 | 0 | 0 | 0 | 0 | CLK3_DLY | CLK3_PWR | CLK3_EN | ||||||||
| R8 | 0 | SYSREF0_PWR_LOW | SYSREF0_AC | 1 | 1 | 1 | SYSREF0_VCM | SYSREF0_PWR | SYSREF0_EN | |||||||
| R9 | 0 | SYSREF1_PWR_LOW | SYSREF1_AC | 1 | 1 | 1 | SYSREF1_VCM | SYSREF1_PWR | SYSREF1_EN | |||||||
| R10 | 0 | SYSREF2_PWR_LOW | SYSREF2_AC | 1 | 1 | 1 | SYSREF2_VCM | SYSREF2_PWR | SYSREF2_EN | |||||||
| R11 | 0 | SYSREF3_PWR_LOW | SYSREF3_AC | 1 | 1 | 1 | SYSREF3_VCM | SYSREF3_PWR | SYSREF3_EN | |||||||
| R12 | 0 | 0 | 0 | LOGICLK_FMT | 0 | 0 | LOGICLK_VCM | LOGICLK_PWR | LOGICLK_EN | |||||||
| R13 | 0 | 0 | 0 | LOGISYSREF_FMT | 0 | 0 | LOGISYSREF_VCM | LOGISYSREF_PWR | LOGISYSREF_EN | |||||||
| R14 | LOGICLK_DIV_RST | 0 | 0 | LOGICLK_DIV | LOGICLK_DIV_PRE | |||||||||||
| R15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LOGICLK2_DIV | LOGICLK2_EN | |
| R16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF_DLY_SCALE | SYSREFREQ_DLY_STEP | SYSREFREQ_VCM_OFFSET | SYSREFREQ_VCM | ||||
| R17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREFREQ_INPUT | SYSWND_UPDATE_STOP | SYNC_STOP | SYSWND_LATCH | SYSREFREQ_CLR | SYSREFREQ_MODE | ||
| R18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREFREQ_DLY | |||||
| R19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF_DLY_BYP | SYSREF_PULSE_CNT | SYSREF_MODE | ||||
| R20 | SYSREF_DLY_DIV | SYSREF_DIV | SYSREF_DIV_PRE | |||||||||||||
| R21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF0_DLY | SYSREF0_DLY_PHASE | |||||||
| R22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF1_DLY | SYSREF1_DLY_PHASE | |||||||
| R23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF2_DLY | SYSREF2_DLY_PHASE | |||||||
| R24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SYSREF3_DLY | SYSREF3_DLY_PHASE | |||||||
| R25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | LOGISYSREF_DLY | LOGISYSREF_DLY_PHASE | |||||||
| R26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SMCLK_DIV | SMCLK_DIV_PRE | SMCLK_EN | |||||
| R27 | 0 | 1 | 1 | 0 | MULT_HIPFD_EN | 1 | FCAL_EN | 0 | 0 | CLK_DIV_RST | CLK_DIV | CLK_MUX | ||||
| R29 | rb_CLKPOS[31:16] | |||||||||||||||
| R30 | rb_CLKPOS[15:0] | |||||||||||||||
| R31 | 0 | 0 | 0 | 0 | 0 | rb_TEMPSENSE | ||||||||||
| R32 | rb_VER_ID | |||||||||||||||
| R36 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 |
| R37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | rb_LOCK_DETECT |
| R39 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| R40 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
| R41 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| R42 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| R43 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
| R44 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| R45 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| R54 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 |
| R55 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | DEV_IOPT_CTRL | |||||
| R77 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |