ZHCSCY6A June 2014 – July 2014 LMK00804B
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 簡化電路原理圖
- 5 修訂歷史記錄
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
-
8 Specifications
- 8.1 Pin Characteristics
- 8.2 Absolute Maximum Ratings
- 8.3 Handling Ratings
- 8.4 Recommended Operating Conditions
- 8.5 Thermal Information
- 8.6 Power Supply Characteristics
- 8.7 LVCMOS / LVTTL DC Characteristics
- 8.8 Differential Input DC Characteristics
- 8.9 Electrical Characteristics (VDDO = 3.3 V ± 5%)
- 8.10 Electrical Characteristics (VDDO = 2.5 V ± 5%)
- 8.11 Electrical Characteristics (VDDO = 1.8 V ± 0.15 V)
- 8.12 Electrical Characteristics (VDDO = 1.5 V ± 5%)
- 8.13 Typical Characteristics
- 9 Parameter Measurement Information
- 10Detailed Description
- 11Applications and Implementation
- 12Power Supply Recommendations
- 13Layout
- 14器件和文檔支持
- 15機械封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PW|16
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
10 Detailed Description
10.1 Overview
The LMK00804B is a low skew, high performance clock fanout buffer which can distribute up to four LVCMOS/LVTTL outputs (3.3-V, 2.5-V, 1.8-V, or 1.5-V levels) from one of two selectable inputs, which can accept differential or single-ended inputs. The clock enable input is synchronized internally to eliminate runt or glitch pulses on the outputs when the clock enable terminal is asserted or de-asserted. The outputs are held in logic low state when the clock is disabled. A separate output enable terminal controls whether the outputs are active state or high-impedance state. The low additive jitter and phase noise floor, and guaranteed output and part-to-part skew characteristics make the LMK00804B ideal for applications demanding high performance and repeatability.
10.2 Functional Block Diagram
10.2.1
10.3 Feature Description
10.3.1 Clock Enable Timing
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 8. In the enabled mode, the output states are a function of the CLK/nCLK or LVCMOS_CLK inputs as described in Clock Input Function.
Figure 8. Clock Enable Timing Diagram
10.4 Device Functional Modes
The device can provide fan-out and level translation from differential or single-ended input to LVCMOS/LVTTL output, where the output VOH and VOL levels are determined by the VDDO output supply voltage and output load condition. Refer to the Clock Input Function.
10.4.1 Clock Input Function
Table 1.
| INPUTS | OUTPUTS | INPUT to OUTPUT MODE | POLARITY | |
|---|---|---|---|---|
| CLK (or LVCMOS_CLK) | nCLK | Qx | ||
| 0 | 1 | LOW | Differential (or Single-Ended) to Single-Ended | Non-inverting |
| 1 | 0 | HIGH | Differential (or Single-Ended) to Single-Ended | Non-inverting |
| 0 | Floating or Biased | LOW | Single-Ended to Single-Ended | Non-inverting |
| 1 | Floating or Biased | HIGH | Single-Ended to Single-Ended | Non-inverting |
| Biased | 0 | HIGH | Single-Ended to Single-Ended | Inverting |
| Biased | 1 | LOW | Single-Ended to Single-Ended | Inverting |