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ZHCSIM9E November 2004 – August 2018 LMH6574

PRODUCTION DATA.

封裝選項

機(jī)械數(shù)據(jù) (封裝 | 引腳)

D|14
- MPDS177H

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics ±5 V

V_S = ±5 V, R_L = 100 Ω, A_V = 2 V/V, R_F = 575 Ω, T_J = 25 °C, unless otherwise specified.

	PARAMETER	TEST CONDITIONS⁽²⁾		MIN	TYP	MAX	UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW	−3 dB Bandwidth	V_OUT = 0.5 V_PP			500		MHz
LSBW	–3 dB Bandwidth	V_OUT = 2 V_PP			400		MHz
.1 dBBW	0. 1 dB Bandwidth	V_OUT = 0.25 V_PP			150		MHz
DG	Differential Gain	R_L = 150 Ω, f = 4.43 MHz			0.02%
DP	Differential Phase	R_L = 150 Ω, f = 4.43 MHz			0.05		deg
XTLK	Channel to Channel Crosstalk	All Hostile, 5 MHz			−85		dB
TIME DOMAIN RESPONSE
TRS	Channel to Channel Switching Time	Logic Transition to 90% Output			8		ns
	Enable and Disable Times	Logic Transition to 90% or 10% Output			10		ns
TRL	Rise and Fall Time	4-V Step			2.4		ns
TSS	Settling Time to 0.05%	2-V Step			17		ns
OS	Overshoot	2-V Step			5%
SR	Slew Rate	4-V Step			2200		V/μs
DISTORTION
HD2	2^ndHarmonic Distortion	2 V_PP , 5 MHz			−68		dBc
HD3	3^rd Harmonic Distortion	2 V_PP , 5 MHz			−84		dBc
IMD	3^rd Order Intermodulation Products	10 MHz, Two Tones 2 V_PP at Output			−80		dBc
EQUIVALENT INPUT NOISE
VN	Voltage	>1 MHz, Input Referred			5		nV√Hz
ICN	Current	>1 MHz, Input Referred			5		pA/√Hz
STATIC, DC PERFORMANCE
CHGM	Channel to Channel Gain Difference	DC, Difference in Gain Between Channels			±0.005%	±0.032%
CHGM	Channel to Channel Gain Difference	DC, Difference in Gain Between Channels	-40°C ≤ T_J ≤ 85°C			±0.035%
VIO	Input Offset Voltage⁽⁵⁾	V_IN = 0 V			1	±20	mV
VIO	Input Offset Voltage⁽⁵⁾	V_IN = 0 V	-40°C ≤ T_J ≤ 85°C			±25	mV
DVIO	Offset Voltage Drift				30		µV/°C
IBN	Input Bias Current⁽⁵⁾⁽⁶⁾	V_IN = 0 V			−3	±5.2	µA
IBN	Input Bias Current⁽⁵⁾⁽⁶⁾	V_IN = 0 V	-40°C ≤ T_J ≤ 85°C			±5.8	µA
DIBN	Bias Current Drift				11		nA/°C
	Inverting Input Bias Current	Pin 12, Feedback Point, V_IN = 0 V			−7	±10
	Inverting Input Bias Current	Pin 12, Feedback Point, V_IN = 0 V	-40°C ≤ T_J ≤ 85°C			±13
PSRR	Power Supply Rejection Ratio⁽⁵⁾	DC, Input Referred		43	54		dB
PSRR	Power Supply Rejection Ratio⁽⁵⁾	DC, Input Referred	-40°C ≤ T_J ≤ 85°C	41			dB
ICC	Supply Current⁽⁵⁾	No Load			13	16	mA
ICC	Supply Current⁽⁵⁾	No Load	-40°C ≤ T_J ≤ 85°C			18	mA
	Supply Current Disabled⁽⁵⁾	ENABLE > 2 V			4.7	6.2	mA
	Supply Current Disabled⁽⁵⁾	ENABLE > 2 V	-40°C ≤ T_J ≤ 85°C			6.3	mA
	Supply Current Shutdown	SHUTDOWN > 2 V			1.8	2.5	mA
	Supply Current Shutdown	SHUTDOWN > 2 V	-40°C ≤ T_J ≤ 85°C			2.6	mA
VIH	Logic High Threshold⁽⁵⁾	Select & Enable Pins (SD & EN)		2.0			V
VIL	Logic Low Threshold⁽⁵⁾	Select & Enable Pins (SD & EN)				0.8	V
IiL	Logic Pin Input Current Low⁽⁶⁾	Logic Input = 0 V Select & Enable Pins (SD & EN)		−3.3	−1		µA
IiL	Logic Pin Input Current Low⁽⁶⁾	Logic Input = 0 V Select & Enable Pins (SD & EN)	-40°C ≤ T_J ≤ 85°C	–9			µA
IiH	Logic Pin Input Current High⁽⁶⁾	Logic Input = 2.0 V, Select & Enable Pins (SD & EN)			47	68	µA
IiH	Logic Pin Input Current High⁽⁶⁾	Logic Input = 2.0 V, Select & Enable Pins (SD & EN)	-40°C ≤ T_J ≤ 85°C			72.5	µA
MISCELLANEOUS PERFORMANCE
RIN+	Input Resistance				5		kΩ
CIN	Input Capacitance				0.8		pF
ROUT	Output Resistance	Output Active, (EN and SD < 0.8 V)			0.04		Ω
ROUT	Output Resistance	Output Disabled, (EN or SD > 2 V)			3000		Ω
COUT	Output Capacitance	Output Disabled, (EN or SD > 2 V)			3.1		pF
VO	Output Voltage Range	No Load		±3.54	±3.7		V
VO		No Load	-40°C ≤ T_J ≤ 85°C	±3.53			V
VOL		R_L = 100 Ω		±3.18	±3.5		V
VOL		R_L = 100 Ω	-40°C ≤ T_J ≤ 85°C	±3.17			V
CMIR	Input Voltage Range			±2.5	±2.6		V
IO	Linear Output Current⁽⁵⁾⁽⁶⁾	V_IN = 0 V		+60	±80		mA
				-70
			-40°C ≤ T_J ≤ 85°C	+50
			-40°C ≤ T_J ≤ 85°C	−60
ISC	Short Circuit Current⁽³⁾	V_IN = ±2 V, Output Shorted to Ground			±230		mA