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ZHCSLH1A September 2021 – December 2021 LMH5485-SP

ADVANCE INFORMATION

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請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

HKX|8

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

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7.5 Electrical Characteristics: V_S+ – V_S– = 5 V

The specifications shown below correspond to the respectively identified subgroup temperature (see Section 7.7), unless otherwise noted. VOCM = open (defaults midsupply), V_OUT = 2 V_PP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 8-1 for an AC-coupled gain of a
2-V/V test circuit, and Figure 8-3 for a DC-coupled gain of a 2-V/V test circuit.

PARAMETER		TEST CONDITIONS		SUBGROUP⁽¹⁾	MIN	TYP	MAX	UNIT
AC PERFORMANCE
	Small-signal bandwidth	Vout = 100 mV_PP, G = 1				530		MHz
	Small-signal bandwidth	Vout = 100 mV_PP, G = 2				490		MHz
	Small-signal bandwidth	Vout = 100 mV_PP, G = 5				240		MHz
	Small-signal bandwidth	Vout = 100 mV_PP, G = 10				125		MHz
GBWP	Gain-bandwidth product	Vout = 100 mV_PP, G = 20				850		MHz
	Large-signal bandwidth	Vout = 2 V_PP				315		MHz
	Bandwidth for 0.1-dB flatness	Vout = 2 V_PP				50		MHz
	Slew rate⁽²⁾	Vout = 2-V_PP, FPBW				1400		V/μs
	Rise/fall time	Vout = 2-V step, input ≤ 0.5 ns t_r				1.4		ns
	Settling time	Vout = 2-V step, t_r = 2 ns	To 1%			5.4		ns
	Settling time	Vout = 2-V step, t_r = 2 ns	To 0.1%			10		ns
	Overshoot and undershoot	Vout = 2-V step, input ≤ 0.3 ns t_r				24%
	100-kHz harmonic distortion	Vout = 2 V_PP	HD2			–111		dBc
	100-kHz harmonic distortion	Vout = 2 V_PP	HD3			–149		dBc
	10-MHz harmonic distortion	Vout = 2 V_PP	HD2			–79		dBc
	10-MHz harmonic distortion	Vout = 2 V_PP	HD3			–97		dBc
	2nd-order intermodulation distortion	f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 V_PP (1 V_PP per tone)				–90		dBc
	3rd-order intermodulation distortion					–85		dBc
	Input voltage noise	f > 100 kHz				2.4		nV/√Hz
	Input current noise	f > 1 MHz				1.9		pA/√Hz
	Overdrive recovery time	2x output overdrive, either polarity				20		ns
	Closed-loop output impedance	f = 10 MHz (differential)				0.1		Ω
DC PERFORMANCE
A_OL	Open-loop voltage gain			[1, 2, 3]	97	119		dB
	Input-referred offset voltage			[1, 2, 3]	–900	±100	900	μV
	Input offset voltage drift⁽³⁾				–2.5	±0.5	2.5	μV/°C
	Input bias current	Positive out of node		[1, 2, 3]	1.7	10	15	μA
	Input bias current drift⁽³⁾					6	15	nA/°C
	Input offset current			[1, 2, 3]	–650	±150	650	nA
	Input offset current drift⁽³⁾				–1.5	±0.3	1.5	nA/°C
INPUT
	Common-mode input low	< 3-dB degradation in CMRR from midsupply		[1, 2, 3]		(Vs–) – 0.2	Vs–	V
	Common-mode input high	< 3-dB degradation in CMRR from midsupply		[1, 2, 3]	(Vs+) – 1.3	(Vs+) –1.2		V
	Common-mode rejection ratio	Input pins at midsupply		[1, 2, 3]	82	100		dB
	Input impedance differential mode	Input pins at midsupply				110 \|\| 1.25		kΩ \|\| pF
OUTPUT
	Output voltage low			[1, 2, 3]		(Vs–) + 0.2	(Vs–) + 0.25	V
	Output voltage high			[1, 2, 3]	(Vs+) – 0.25	(Vs+) – 0.2		V
	Output current drive			[1, 2, 3]	±75	±100		mA
POWER SUPPLY
	Specified operating voltage			[1, 2, 3]	2.7	5	5.1	V
	Quiescent operating current			[1, 2, 3]	9.2	10.1	11	mA
±PSRR	Power-supply rejection ratio	Either supply pin to differential Vout		[1, 2, 3]	82	100		dB
POWER DOWN
	Enable voltage threshold			[1, 2, 3]	(Vs–) + 1.7			V
	Disable voltage threshold			[1, 2, 3]			(Vs–) + 0.7	V
	Disable pin bias current	PD = Vs– → Vs+		[1, 2, 3]		20	50	nA
	Power-down quiescent current	PD = (Vs–) + 0.7 V		[1, 2, 3]		6	30	μA
	Power-down quiescent current	PD = Vs–		[1, 2, 3]		2	8	μA
	Turnon-time delay	Time from PD = low to Vout = 90% of final value				100		ns
	Turnoff time delay	Time from PD = low to Vout = 10% of final value				60		ns
OUTPUT COMMON-MODE VOLTAGE CONTROL⁽⁴⁾
	Small-signal bandwidth	Vocm = 100 mV_PP				150		MHz
	Slew rate⁽²⁾	Vocm = 2-V step				400		V/μs
	Gain			[1, 2, 3]	0.975	0.982	0.995	V/V
	Input bias current	Considered positive out of node		[1, 2, 3]	–0.8	0.1	0.8	μA
	Input impedance	Vocm input driven to midsupply				47 \|\| 1.2		kΩ \|\| pF
	Default voltage offset from midsupply	Vocm pin open		[1, 2, 3]	–45	±8	45	mV
CM Vos	Common-mode offset voltage	Vocm input driven to midsupply		[1, 2, 3]	–8	±2	8	mV
	CM V_OS drift⁽³⁾	Vocm input driven to midsupply			–20	±4	+20	mV/°C
	Common-mode loop supply headroom to negative supply	< ±15-mV shift from midsupply CM Vos		[1, 2, 3]	0.94			V
	Common-mode loop supply headroom to positive supply	< ±15-mV shift from midsupply CM Vos		[1, 2, 3]	1.2			V

(1) For subgroup definitions, please see Section 7.7

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_P / √2) · 2π · f_–3dB.

(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end-points, computing the difference, and dividing by the temperature range.

(4) Specifications are from the input Vocm pin to the differential output average voltage.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

7.5 Electrical Characteristics: VS+ – VS– = 5 V

7.5 Electrical Characteristics: V_S+ – V_S– = 5 V