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ZHCSPC5 October 2022 LM51231-Q1

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RGR|20
- MPQF239A

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RGR|20
- QFND664

訂購信息

zhcspc5_oa

6.5 Electrical Characteristics

Typical values correspond to T_J= 25 °C. Minimum and maximum limits apply over T_J= -40 °C to 125 °C. Unless otherwise stated, V_BIAS= 12 V, V_VOUT= 12 V, R_T= 9.09 kΩ, , R_VREF = 65 kΩ

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT(BIAS, VCC, VOUT)
I_BIAS-SD	BIAS current in shutdown	V_UVLO= 0 V, V_OUT= 11.3 V		2.5	5	μA
I_BIAS-ACTIVE	BIAS current in active (Non-switching, VCC is supplied by BIAS)	V_UVLO= 2.5 V, V_TRK = 0.6 V		1.22	1.52	mA
I_BIAS-BYP	BIAS current in bypass mode	V_UVLO= 2.5 V, V_TRK = 0.25 V		1.22	1.52	mA
I_VOUT-SD	VOUT current in shutdown	V_UVLO= 0 V, V_OUT= 11.3 V			1	μA
I_VOUT-BYP-DE	VOUT current in bypass mode	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_VOUT= 12 V, MODE = GND		100	115	μA
I_{VOUT-BYP-FPWM}	VOUT current in bypass mode	V_UVLO= 2.5 V, V_TRK = 0.25 V, V_VOUT= 12 V, MODE = VCC		240	276	μA
I_VOUT-ACTIVE	VOUT current in active (Non-switching) (DE mode)	V_UVLO= 2.5 V, V_TRK = 0.6 V, MODE = GND		90	105	μA
I_VOUT-ACTIVE	VOUT current in active (Non-switching), (FPWM)	V_UVLO= 2.5 V, V_TRK = 0.6 V, MODE = VCC		240	276	μA
I_BATTERY-SD	Battery drain in shutdown	V_UVLO= 0 V, V_OUT= 11.3 V		2.5	5	μA
I_BATTERY-DE	Battery drain in bypass mode (DE mode)	V_UVLO= 2.5 V, V_TRK = 0.25 V, MODE = GND		1.44	1.59	mA
I_BATTERY-FPWM	Battery drain in bypass mode (FPWM)	V_UVLO= 2.5 V, V_TRK = 0.25 V, MODE = VCC		1.58	1.74	mA
ENABLE, UVLO
V_EN-RISING	Enable threshold	EN rising	0.45	0.55	0.65	V
V_EN-FALLING	Enable threshold	EN falling	0.35	0.45	0.55	V
V_EN-HYS	Enable hysteresis	EN falling	55	90	130	mV
I_UVLO-HYS	UVLO pull-down hysteresis current	V_UVLO = 0.7 V	8	10	12	μA
V_UVLO-RISING	UVLO threshold	UVLO rising	1.05	1.1	1.15	V
V_UVLO-FALLING	UVLO threshold	UVLO falling	1.025	1.075	1.125	V
V_UVLO-HYS	UVLO hysteresis	UVLO falling		25		mV
SYNC/DITHER/VH
V_SYNC-RISING	SYNC threshold/SYNC detection threshold	SYNC rising			2	V
V_SYNC-FALLING	SYNC threshold	SYNC falling	0.4			V
	Minimum SYNC pull up pulse width				100	ns
I_DITHER	Dither source/sink current		16	21	26	μA
Δf_SW1	f_SW Modulation (Upper Limit)			5%
Δf_SW2	f_SWModulation (Lower Limit)			-6%
V_{DITHER-FALLING}	Dither disable threshold		0.65	0.75	0.85	V
VCC
V_VCC-REG1	VCC regulation	I_VCC= 100 mA	4.75	5	5.25	V
V_VCC-REG2	VCC regulation	No load	4.75	5	5.25	V
V_VCC-REG3	VCC regulation during dropout	V_BIAS= 3.8V, I_VCC= 100 mA	3.45			V
V_{VCC-UVLO-RISING}	VCC UVLO threshold	VCC rising	3.55	3.65	3.75	V
V_{VCC-UVLO-FALLING}	VCC UVLO threshold	VCC falling	3.2	3.3	3.4	V
I_VCC-CL	VCC sourcing current limit	V_VCC = 4 V	100			mA
CONFIGURATION (MODE)
V_MODE-RISING	FPWM mode threshold	MODE rising			2.0	V
V_MODE-FALLING	Diode emulation mode threshold	MODE falling	0.4			V
RT
V_RT	RT regulation			0.5		V
VREF, TRK, VOUT
V_REF	VREF regulation target		0.99	1	1.005	V
V_OUT-REG	VOUT regulation target1 with resistor divider (lower VOUT range)	VREF resistor divider to make V_TRK = 0.25 V, R_VREF = 65 kΩ	4.915	5	5.085	V
V_OUT-REG	VOUT regulation target2 with resistor divider (lower VOUT range)	VREF resistor divider to make V_TRK = 0.5 V, R_VREF = 65 kΩ	9.9	10	10.1	V
V_OUT-REG	VOUT regulation target3 with resistor divider (lower VOUT range)	VREF resistor divider to make V_TRK = 1.0 V, R_VREF = 65 kΩ	19.8	20	20.2	V
V_OUT-REG	VOUT regulation target4 with resistor divider (upper VOUT range)	VREF resistor divider to make V_TRK = 0.25 V, R_VREF = 35 kΩ	14.74	15	15.24	V
V_OUT-REG	VOUT regulation target5 with resistor divider (upper VOUT range)	VREF resistor divider to make V_TRK = 0.5 V, R_VREF = 35 kΩ	29.7	30	30.3	V
V_OUT-REG	VOUT regulation target6 with resistor divider (upper VOUT range)	VREF resistor divider to make V_TRK = 0.95 V, R_VREF = 35 kΩ	56.43	57	57.57	V
V_OUT-REG	VOUT regulation target1 using TRK (lower VOUT range)	V_TRK = 0.25 V, R_VREF = 65 kΩ	4.91	5	5.09	V
V_OUT-REG	VOUT regulation target2 using TRK (lower VOUT range)	V_TRK = 0.5 V, R_VREF = 65 kΩ	9.88	10	10.11	V
V_OUT-REG	VOUT regulation target3 using TRK (lower VOUT range)	V_TRK = 1.0 V, R_VREF = 65 kΩ	19.8	20	20.2	V
V_OUT-REG	VOUT regulation target4 using TRK (upper VOUT range)	V_TRK = 0.25 V, R_VREF = 35 kΩ	14.71	15	15.25	V
V_OUT-REG	VOUT regulation target5 using TRK (upper VOUT range)	V_TRK = 0.5 V, R_VREF = 35 kΩ	29.6	30	30.3	V
V_OUT-REG	VOUT regulation target6 using TRK (upper VOUT range)	V_TRK = 0.95 V, R_VREF = 35 kΩ	56.45	57	57.5	V
I_TRK	TRK bias current				1	μA
SOFT START, DE to FPWM TRANSITION
I_SS	Soft-start current		17	20	23	μA
V_SS-DONE	MODE transition start	SS rising	1.3	1.5	1.7	V
R_SS	SS pull-down switch R_DSON			30	70	Ω
V_SS-DIS	SS discharge detection threshold		30	50	75	mV
V_SS-FB	internal SS to FB clamp	V_FB=0V		55	75	mV
CURRENT SENSE (CSP, CSN, SW, SENSE)
V_SLOPE	Peak slope compensation amplitude	R_T = 220 kΩ, Referenced to CS input		45		mV
A_CS	Current sense amplifier gain	CSP=3.0V		10		V/V
A_CS	Current sense amplifier gain	CSP=1.5V		10		V/V
V_CLTH	Positive peak current limit threshold (CSP-CSN)	CSP=3.0V, MODE = GND	52	60	68	mV
V_CLTH	Positive peak current limit threshold (CSP-CSN)	CSP=1.5V, MODE = GND	51	60	72	mV
V_ZCD-DE	ZCD threshold (SW-SENSE)	MODE = GND		4		mV
V_I-NEG-FPWM	Negative current limit threshold (SW-SENSE)	MODE = VCC		–150		mV
V_CS-FWD	Forward current threshold voltage to enter bypass mode (CSP-CSN)	V_ULVO = 2.5 V, V_TRK = 0.25 V	2	6	10	mV
V_ZCD-BYP	Zero cross detection in bypass mode (DE mode) (SW-SENSE)	V_ULVO = 2.5 V, V_TRK = 0.25 V, MODE = GND		-5		mV
V_I-NEG-BYP	Negative current limit in bypass mode (FPWM) (SW-SENSE)	V_ULVO = 2.5 V, V_TRK = 0.25 V, MODE = VCC		-150		mV
I_CSN	CSN bias current				1	μA
I_CSP	CSP bias current			110		μA
BOOT FAULT PROTECTION (HB)
	Maximum replenish pulse cycles			4		cycles
	Replenish off cycles			12		cycles
	Number of sets to enter hiccup mode protection			4		sets
	Off-cycle during hiccup mode off			512		cycles
ERROR AMPLIFIER (COMP)
Gm	Transconductance			1		mA/V
I_SOURCE-MAX	Maximum COMP sourcing current	V_COMP=0V	95			μA
I_SINK-MAX	Maximum COMP sinking current	V_COMP=1.8V	90			μA
V_CLAMP-MAX	COMP maximum clamp voltage	COMP rising	2.05	2.4	2.8	V
V_CLAMP-MIN	COMP minimum clamp voltage	COMP falling		0.65		V
PULSE WIDTH MODULATION (PWM)
f_SW1	Switching frequency	R_T = 220 kΩ	85	100	115	kHz
f_SW2	Switching frequency	R_T = 9.09 kΩ	1980	2200	2420	kHz
t_ON-MIN	Minimum controllable on-time	R_T = 9.09 kΩ	14	20	50	ns
t_OFF-MIN	Minimum forced off-time	R_T = 9.09 kΩ	70	95	115	ns
D_MAX1	Maximum duty cycle limit	R_T = 220kΩ	90%	94%	98%
D_MAX2	Maximum duty cycle limit	R_T = 9.09 kΩ	75%	80%	83%
PGOOD, OVP
V_OVTH-RISING	Overvoltage threshold (OVP threshold)	VOUT rising (referenced to V_OUT-REG)	108.5%	110%	113.5%
V_OVTH-FALLING	Overvoltage threshold (OVP threshold)	VOUT falling (referenced to V_OUT-REG)	100.5%	103%	105.5%
V_OVTH-DLY	Delay before entering bypass mode			30		us
V_UVTH-RISING	Undervoltage threshold (PGOOD threshold)	VOUT rising (referenced to V_OUT-REG)	91.5%	94%	98%
V_UVTH-FALLING	Undervoltage threshold (PGOOD threshold)	VOUT falling (referenced to V_OUT-REG)	89.5%	92%	95.5%
	UV comparator deglitch filter	Rising edge		26		μs
	UV comparator deglitch filter	Falling edge		21		μs
R_PGOOD	PGOOD pull-down switch R_DSON			90	180	Ω
	Minimum BIAS for valid PGOOD				2.5	V
MOSFET DRIVER
	High-state voltage drop (HO driver)	100mA sinking		0.08	0.15	V
	Low-state voltage drop (HO driver)	100mA sourcing		0.04	0.1	V
	High-state voltage drop (LO driver)	100mA sinking		0.08	0.17	V
	Low-state voltage drop (LO driver)	100mA sourcing		0.04	0.1	V
V_HB-UVLO	HB-SW UVLO threshold	HB-SW falling	2.2	2.5	3.0	V
t_DHL	HO off to LO on deadtime			20		ns
t_DLH	LO off to HO on deadtime			22		ns
	HB diode resistance			1.2		Ω
I_CP	HB charge pump current	BIAS=3.8V	30	55		μA
THERMAL SHUTDOWN
T_TSD-RISING	Thermal shutdown threshold	Temperature rising		175		°C
T_TSD-HYS	Thermal shutdown hysteresis			15		°C