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ZHCSCJ2 June 2014 LM3633

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

YFQ|20
- MXBG174

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcscj2_oa

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V_IN to GND	−0.3	6	V
V_SW, V_OVP, V_HVLED1, V_HVLED2, V_HVLED3 to GND	−0.3	45
V_SCL, V_SDA, V_PWM to GND	−0.3	6
V_HWEN, V_CPOUT to GND, V_C–, V_C+	−0.3	6
V_LVLED1- V_LVLED6, to GND	−0.3	6
Continuous power dissipation		Internally Limited
Junction temperature (T_J-MAX)		150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		−65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	−1000	1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	−250	250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
V_IN to GND	2.7	5.5	V
V_SW, V_OVP, V_HVLED1, V_VHLED2, V_VHLED3 to GND, V_PWM, V_HWEN, V_SDA, V_SCL	0	40
V_LVLED1- V_LVLED6 to GND	0	6
Junction temperature (T_J) ⁽¹⁾⁽²⁾	−40	125	°C

(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J= 140°C (typ.) and disengages at T_J= 125°C (typ.).

(2) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP = 125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the following equation: T_A-MAX = T_J-MAX-OP – (θ_JA × P_D-MAX).

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		DSBGA	UNIT
THERMAL METRIC⁽¹⁾		(20 PINS)	UNIT
R_θJA	Thermal resistance junction-to-ambient	55.3	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Limits apply over the full operating ambient temperature range (−40°C ≤ T_A ≤ 85°C) and V_IN = 3.6 V, unless otherwise specified.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (IN PIN)
I_SHDN	Shutdown current	2.7 V ≤ V_IN ≤ 5.5 V, HWEN = GND			1	5.5	µA
THERMAL SHUTDOWN
T_SD	Thermal shutdown				140		°C
T_SD	Hysteresis				15		°C
BOOST CONVERTER AND HVLED
I_HVLED(1/2/3)	Output current regulation (HVLED1, HVLED2 or HVLED3)	Full-scale current = 20.2 mA, PWM off, brightness code = max, exponential mapping, auto headroom off, HVLED1 Bank A, HVLED2/3 Bank B	2.7 V ≤ V_IN ≤ 5.5 V	18.38 (–9%)	20.2	22.02 (9%)	mA
		Full-scale current = 20.2 mA, PWM off, brightness code = max, exponential mapping, auto headroom off, HVLED1 Bank A, HVLED2/3 Bank B	T_A = 25°C	–3.4%	±2.0%	3.2%
			T_A = 25°C, 3.0 V ≤ V_IN ≤ 4.5 V	–3.6%		3.4%
			T_A = 25°C		±2.0%
I_{MATCH_HV}	HVLED1 to HVLED2 or HVLED3 matching ⁽³⁾	PWM off, exponential mapping, auto headroom off HVLED1,2,3 = Bank A,	2.7 V ≤ V_IN ≤ 5.5 V, I_LED = 20.2 mA	–2.5%		2.5%
			T_A = 25°C, I_LED = 20.2 mA	–2.0%		1.7%
			2.7 V ≤ V_IN ≤ 5.5 V I_LED = 500 µA	–8.5%		8.5%
I_{LED_MIN}	Minimum LED current	Full-scale current = 20.2 mA, Exponential Mapping			6.0		µA
V_{REG_CS}	Regulated current sink headroom voltage	Auto headroom off, T_A = 25°C			400		mV
V_{HR_HV}	Minimum current sink headroom voltage for HVLED current sinks	I_LED = 95% of nominal, full-scale current = 20.2 mA, auto headroom off	2.7 V ≤ V_IN ≤ 5.5 V			285
V_{HR_HV}			T_A = 25°C		190
R_DSON	NMOS switch on resistance	I_SW = 500 mA, T_A = 25°C			0.3		Ω
I_{CL_BOOST}	NMOS switch current limit			880		1120	mA
I_{CL_BOOST}	NMOS switch current limit	T_A = 25°C			1000		mA
V_OVP	Output overvoltage protection	ON threshold OVP select bits = 11	2.7 V ≤ V_IN ≤ 5.5 V	38.75		41.1	V
		ON threshold OVP select bits = 11	T_A = 25°C		40
		Hysteresis	T_A = 25°C		1
f_SW	Switching frequency	Boost frequency select bit = 0	2.7 V ≤ V_IN ≤ 5.5 V	450		550	kHz
		Boost frequency select bit = 0	T_A = 25°C		500
		Boost frequency select bit = 1	2.7 V ≤ V_IN ≤ 5.5 V	900		1100
		Boost frequency select bit = 1	T_A = 25°C		1000
D_MAX	Maximum duty cycle	2.7 V ≤ V_IN ≤ 5.5 V			94%
CHARGE PUMP AND LVLED
I_{LVLED(1/2/3/4/5/6)}	Output current regulation (low-voltage current sinks)	Full-scale current = 20.2 mA, brightness code = 0xFF	2.7 V ≤ V_IN ≤ 5.5 V	18.38	20.2	22.02	mA
I_{MATCH_LV}	LVLED current sink matching ⁽⁴⁾	Full-scale current = 20.2 mA	2.7 V ≤ V_IN ≤ 5.5 V	−3.1%		2%
V_{HR_LV}	Minimum current sink headroom voltage for LVLED current sinks	I_LED = 95% of nominal, full-scale current = 20.2 mA				125	mV
V_{HR_LV}		I_LED = 95% of nominal, full-scale current = 20.2 mA	T_A = 25°C		80
V_GTH	Threshold for gain transition	2.7 V ≤ V_IN ≤ 5.5 V		65		190
V_GTH	Threshold for gain transition		T_A = 25°C		125
V_CPOUT	Charge Pump Output Voltage	2X Gain	T_A = 25°C		4.42		V
I_{CL_PUMP}	Charge pump current limit	1X Gain, output referred	3 V ≤ V_IN ≤ 5.5 V	180	350		mA
I_{CL_PUMP}	Charge pump current limit	2X Gain	T_A = 25°C		240		mA
R_OUT	Charge pump output resistance	1X Gain	T_A = 25°C		1.1		Ω
HWEN INPUT
V_{HWEN_L}	Logic low	2.7 V ≤ V_IN ≤ 5.5 V		0		0.4	V
V_{HWEN_H}	Logic High	2.7 V ≤ V_IN ≤ 5.5 V		1.2		V_IN	V
PWM INPUT
V_{PWM_L}	Input logic low	2.7 V ≤ V_IN ≤ 5.5 V		0		400	mV
V_{PWM_H}	Input logic high	2.7 V ≤ V_IN ≤ 5.5 V		1.36		V_IN	mV
t_PWM	Minimum PWM input pulse	2.7 V ≤ V_IN ≤ 5.5 V, PWM Zero Detect Enabled				0.75	µs
I²C-COMPATIBLE VOLTAGE SPECIFICATIONS (SCL, SDA)
V_IL	Input logic low	2.7 V ≤ V_IN ≤ 5.5 V		0		400	mV
V_IH	Input logic high	2.7 V ≤ V_IN ≤ 5.5 V		1.35		V_IN	V
V_OL	Output logic low (SDA)	2.7 V ≤ V_IN ≤ 5.5 V, I_LOAD = 3 mA				400	mV

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum and Maximum limits are verified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but do represent the most likely norm. Unless otherwise specified, conditions for typical specifications are: V_IN = 3.6 V and T_A = 25°C.

(3) LED current sink matching in the high-voltage current sinks (HVLED1 through HVLED3) is given as the maximum matching value between any two current sinks, where the matching between any two high voltage current sinks (X and Y) is given as (I_HVLEDX ( or I_HVLEDY) - I_AVE(X-Y))/(I_AVE(X-Y)) x 100. In this test all three HVLED current sinks are assigned to Bank A.

(4) LED current sink matching in the low-voltage current sinks (LVLED1 through LVLED3 or LVLED4 through LVLED6) is given as the maximum matching value between any two current sinks, where the matching between any two low voltage current sinks (X and Y) is given as (I_LVLEDX ( or I_LVLEDY) - I_AVE(X-Y))/(I_AVE(X-Y)) x 100. In this test LVLED1-3 current sinks are assigned to Bank C and LVLED4-6 are assigned to Bank F.

6.6 Timing Requirements

Limits apply over the full operating ambient temperature range (−40°C ≤ T_A ≤ 85°C) and V_IN = 3.6 V, unless otherwise specified.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
I²C-COMPATIBLE TIMING SPECIFICATIONS (SCL, SDA)⁽³⁾, Figure 1
t₁	SCL (Clock Period)	2.7 V ≤ V_IN ≤ 5.5 V		2.5		µs
t₂	Data In setup time to SCL high	2.7 V ≤ V_IN ≤ 5.5 V		100		ns
t₃	Data out stable after SCL low	2.7 V ≤ V_IN ≤ 5.5 V		0
t₄	SDA low setup time to SCL low (Start)	2.7 V ≤ V_IN ≤ 5.5 V		100
t₅	SDA high hold time after SCL high (Stop)	2.7 V ≤ V_IN ≤ 5.5 V		100
INTERNAL POR THRESHOLD AND HWEN TIMING SPECIFICATION
V_POR	POR reset release voltage threshold	VIN ramp time = 100 μs	1.7		2.1	V
V_POR	POR reset release voltage threshold	VIN ramp time = 100 μs, T_A = 25°C		1.9		V
t_HWEN	First I²C start pulse after HWEN high	POR reset complete, 2.7 V ≤ V_IN ≤ 5.5 V			20	µs
t_HWEN	First I²C start pulse after HWEN high	POR reset complete, T_A = 25°C		5		µs