ZHCSNC7 December 2021 LM25148
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Input Voltage Range (VIN)
- 8.3.2 High-Voltage Bias Supply Regulator (VCC, VCCX, VDDA)
- 8.3.3 Precision Enable (EN)
- 8.3.4 Power-Good Monitor (PG)
- 8.3.5 Switching Frequency (RT)
- 8.3.6 Dual Random Spread Spectrum (DRSS)
- 8.3.7 Soft Start
- 8.3.8 Output Voltage Setpoint (FB)
- 8.3.9 Minimum Controllable On Time
- 8.3.10 Error Amplifier and PWM Comparator (FB, EXTCOMP)
- 8.3.11 Slope Compensation
- 8.3.12 Inductor Current Sense (ISNS+, VOUT)
- 8.3.13 Hiccup Mode Current Limiting
- 8.3.14 High-Side and Low-Side Gate Drivers (HO, LO)
- 8.3.15 Output Configurations (CNFG)
- 8.3.16 Single-Output Dual-Phase Operation
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Design 1 – High Efficiency 2.1-MHz Synchronous
Buck Regulator
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Custom Design With WEBENCH? Tools
- 9.2.1.2.2 Custom Design With Excel Quickstart Tool
- 9.2.1.2.3 Buck Inductor
- 9.2.1.2.4 Current-Sense Resistance
- 9.2.1.2.5 Output Capacitors
- 9.2.1.2.6 Input Capacitors
- 9.2.1.2.7 Frequency Set Resistor
- 9.2.1.2.8 Feedback Resistors
- 9.2.1.2.9 Compensation Components
- 9.2.1.3 Application Curves
- 9.2.2 Design 2 – High Efficiency 440-kHz Synchronous Buck Regulator
- 9.2.3 Design 3 – Dual-Phase 400-kHz 20-A Synchronous Buck Regulator
- 9.2.1
Design 1 – High Efficiency 2.1-MHz Synchronous
Buck Regulator
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGY|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGY|24
訂購信息
11.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuit (with high current and voltage slew rates) to achieve a robust and reliable design. As expected, certain issues must be considered before designing a PCB layout using the LM25148. The high-frequency power loop of a buck regulator power stage is denoted by loop 1 in the shaded area of Figure 11-1. The topological architecture of a buck regulator means that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important are the gate drive loops of the high-side and low-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1.
Figure 11-1 DC/DC Regulator Ground System With Power Stage and Gate Drive Circuit Switching Loops