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ZHCSGD0 June 2017 LM25145

PRODUCTION DATA.

封裝選項(xiàng)

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGY|20

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsgd0_oa

7 Specifications

7.1 Absolute Maximum Ratings

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted).⁽¹⁾

		MIN	MAX	UNIT
Input voltages	VIN	–0.3	45	V
	SW	–1	45
	SW (20-ns transient)	–5	45
	ILIM	–1	45
	EN/UVLO	–0.3	45
	VCC	–0.3	14
	FB, COMP, SS/TRK, RT	–0.3	6
	SYNCIN	–0.3	14
Output voltages	BST	–0.3	60	V
	BST to VCC		45
	BST to SW	–0.3	14
	VCC to BST (20-ns transient)		7
	LO (20-ns transient)	–3
	PGOOD	–0.3	14
Operating junction temperature, T_J			150	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted).⁽¹⁾

			MIN	MAX	UNIT
V_I	Input voltages	VIN	6	42	V
		SW	–1	42
		ILIM	–1	42
		External VCC bias rail	8	13
		EN/UVLO	0	42
V_O	Output voltages	BST	–0.3	55	V
		BST to VCC		42
		BST to SW	5	13
		PGOOD		13
I_SINK, I_SRC	Sink/source currents	SYNCOUT	–1	1	mA
I_SINK, I_SRC	Sink/source currents	PGOOD		2	mA
T_J	Operating junction temperature		–40	125	°C

(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM25145	UNIT
		RGY (VQFN)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	36.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	28	°C/W
R_θJB	Junction-to-board thermal resistance	11.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	11.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

Typical values correspond to T_J = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. V_IN = 24 V, V_EN/UVLO = 1.5 V, R_RT = 25 kΩ unless otherwise stated.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY
V_IN	Operating input voltage range		6		42	V
I_Q-RUN	Operating input current, not switching	V_EN/UVLO = 1.5 V, V_SS/TRK = 0 V		1.8	2.1	mA
I_Q-STBY	Standby input current	V_EN/UVLO = 1 V		1.75	2	mA
I_Q-SDN	Shutdown input current	V_EN/UVLO = 0 V, V_VCC < 1 V		13.5	16	µA
VCC REGULATOR
V_VCC	VCC regulation voltage	V_SS/TRK = 0 V, 9 V ≤ V_VIN ≤ 42 V, 0 mA < I_VCC ≤ 20 mA	7.3	7.5	7.7	V
V_VCC-LDO	VIN to VCC dropout voltage	V_VIN = 6 V, V_SS/TRK = 0 V, I_VCC = 20 mA		0.25	0.63	V
I_SC-LDO	VCC short-circuit current	V_SS/TRK = 0 V, V_VCC = 0 V	40	50	70	mA
V_VCC-UV	VCC undervoltage threshold	V_VCC rising	4.8	4.93	5.2	V
V_VCC-UVH	VCC undervoltage hysteresis	Rising threshold – falling threshold		0.26		V
V_VCC-EXT	Minimum external bias supply voltage	Voltage required to disable VCC regulator	8			V
I_VCC	External VCC input current, not switching	V_SS/TRK = 0 V, V_VCC = 13 V			2.1	mA
ENABLE AND INPUT UVLO
V_SDN	Shutdown to standby threshold	V_EN/UVLO rising		0.42		V
V_SDN-HYS	Shutdown threshold hysteresis	EN/UVLO rising – falling threshold		50		mV
V_EN	Standby to operating threshold	V_EN/UVLO rising	1.164	1.2	1.236	V
I_EN-HYS	Standby to operating hysteresis current	V_EN/UVLO = 1.5 V	9	10	11	µA
ERROR AMPLIFIER
V_REF	FB reference voltage	FB connected to COMP	792	800	808	mV
I_FB-BIAS	FB input bias current	V_FB = 0.8 V	–0.1		0.1	µA
V_COMP-OH	COMP output high voltage	V_FB = 0 V, COMP sourcing 1 mA		5		V
V_COMP-OL	COMP output low voltage	COMP sinking 1 mA			0.3	V
AVOL	DC gain			94		dB
GBW	Unity gain bandwidth			6.5		MHz
SOFT-START AND VOLTAGE TRACKING
I_SS	SS/TRK capacitor charging current	V_SS/TRK = 0 V	8.5	10	12	µA
R_SS	SS/TRK discharge FET resistance	V_EN/UVLO = 1 V, V_SS/TRK = 0.1 V		11		Ω
V_SS-FB	SS/TRK to FB offset		–15		15	mV
V_SS-CLAMP	SS/TRK clamp voltage	V_SS/TRK – V_FB, V_FB = 0.8 V		115		mV
POWER GOOD INDICATOR
PG_UTH	FB upper threshold for PGOOD high to low	% of V_REF, V_FB rising	106%	108%	110%
PG_LTH	FB lower threshold for PGOOD high to low	% of V_REF, V_FB falling	90%	92%	94%
PG_{HYS_U}	PGOOD upper threshold hysteresis	% of V_REF		3%
PG_{HYS_L}	PGOOD lower threshold hysteresis	% of V_REF		2%
T_PG-RISE	PGOOD rising filter	FB to PGOOD rising edge		25		µs
T_PG-FALL	PGOOD falling filter	FB to PGOOD falling edge		25		µs
V_PG-_OL	PGOOD low state output voltage	V_FB = 0.9 V, I_PGOOD = 2 mA			150	mV
I_PG-OH	PGOOD high state leakage current	V_FB = 0.8 V, V_PGOOD = 13 V			100	nA
OSCILLATOR
F_SW1	Oscillator Frequency – 1	R_RT = 100 kΩ		100		kHz
F_SW2	Oscillator Frequency – 2	R_RT = 25 kΩ	380	400	420	kHz
F_SW3	Oscillator Frequency – 3	R_RT = 12.5 kΩ		780		kHz
SYNCHRONIZATION INPUT AND OUTPUT
F_SYNC	SYNCIN external clock frequency range	% of nominal frequency set by R_RT	–20%		+50%
V_SYNC-IH	Minimum SYNCIN input logic high		2			V
V_SYNC-IL	Maximum SYNCIN input logic low				0.8	V
R_SYNCIN	SYNCIN input resistance	V_SYNCIN = 3 V		20		kΩ
T_SYNCI-PW	SYNCIN input minimum pulsewidth	Minimum high state or low state duration	50			ns
V_SYNCO-OH	SYNCOUT high state output voltage	I_SYNCOUT = –1 mA (sourcing)	3			V
V_SYNCO-OL	SYNCOUT low state output voltage	I_SYNCOUT = 1 mA (sinking)			0.4	V
T_SYNCOUT	Delay from HO rising to SYNCOUT leading edge	V_SYNCIN = 0 V, T_S = 1/F_SW, F_SW set by R_RT	T_S/2 – 140			ns
T_SYNCIN	Delay from SYNCIN leading edge to HO rising	50% to 50%		150		ns
BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD
V_BST-FWD	Diode forward voltage, VCC to BST	VCC to BST, BST pin sourcing 20 mA		0.75	0.9	V
I_Q-BST	BST to SW quiescent current, not switching	V_SS/TRK = 0 V, V_SW = 24 V, V_BST = 30 V		80		µA
V_BST-UV	BST to SW undervoltage detection	V_BST – V_SW falling		3.4		V
V_BST-HYS	BST to SW undervoltage hysteresis	V_BST – V_SW rising		0.42		V
PWM CONTROL
T_ON(MIN)	Minimum controllable on-time	V_BST – V_SW = 7 V, HO 50% to 50%		40	60	ns
T_OFF(MIN)	Minimum off-time	V_BST – V_SW = 7 V, HO 50% to 50%		140	200	ns
DC_100kHz	Maximum duty cycle	F_SW = 100 kHz, 6 V ≤ V_VIN ≤ 42 V	98%	99%
DC_400kHz	Maximum duty cycle	F_SW = 400 kHz, 6 V ≤ V_VIN ≤ 42 V	90%	94%
V_RAMP(min)	Ramp valley voltage (COMP at 0% duty cycle)			300		mV
k_FF	PWM feedforward gain (V_IN / V_RAMP)	6 V ≤ V_VIN ≤ 42 V		15		V/V
OVERCURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING
I_RS	ILIM source current, R_SENSE mode	Low voltage detected at ILIM	90	100	110	µA
I_RDSON	ILIM source current, R_DS(on) mode	SW voltage detected at ILIM, T_J = 25°C	180	200	220	µA
I_RSTC	ILIM current tempco	R_DS-ON mode		4500		ppm/°C
I_RDSONTC	ILIM current tempco	R_SENSE mode		0		ppm/°C
V_ILIM-TH	ILIM comparator threshold at ILIM		–8	–2	3.5	mV
SHORT-CIRCUIT PROTECT (SCP) – DUTY CYCLE CLAMP
V_CLAMP-OS	Clamp offset voltage – no current limiting	CLAMP to COMP steady state offset voltage	0.2 + V_VIN/75			V
V_CLAMP-MIN	Minimum clamp voltage	CLAMP voltage with continuous current limiting	0.3 + V_VIN/150			V
HICCUP MODE FAULT PROTECTION
C_HICC-DEL	Hiccup mode activation delay	Clock cycles with current limiting before hiccup off-time activated		128		cycles
C_HICCUP	Hiccup mode off-time after activation	Clock cycles with no switching followed by SS/TRK release		8192		cycles
DIODE EMULATION
V_ZCD-SS	Zero-cross detect (ZCD) soft-start ramp	ZCD threshold measured at SW pin 50 clock cycles after first HO pulse		0		mV
V_ZCD-_DIS	Zero-cross detect disable threshold (CCM)	ZCD threshold measured at SW pin 1000 clock cycles after first HO pulse		200		mV
V_DEM-TH	Diode emulation zero-cross threshold	Measured at SW with V_SW rising	–5	0	5	mV
GATE DRIVERS
R_HO-UP	HO high-state resistance, HO to BST	V_BST – V_SW = 7 V, I_HO = –100 mA		1.5		Ω
R_HO-DOWN	HO low-state resistance, HO to SW	V_BST – V_SW = 7 V, I_HO = 100 mA		0.9		Ω
R_LO-UP	LO high-state resistance, LO to VCC	V_BST – V_SW = 7 V, I_LO= –100 mA		1.5		Ω
R_LO-DOWN	LO low-state resistance, LO to PGND	V_BST – V_SW = 7 V, I_LO = 100 mA		0.9		Ω
I_HOH, I_LOH	HO, LO source current	V_BST – V_SW = 7 V, HO = SW, LO = AGND		2.3		A
I_HOL, I_LOL	HO, LO sink current	V_BST – V_SW = 7 V, HO = BST, LO = VCC		3.5		A
THERMAL SHUTDOWN
T_SD	Thermal shutdown threshold	T_J rising		175		°C
T_SD-HYS	Thermal shutdown hysteresis			20		°C

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

(2) The junction temperature (T_J in °C) is calculated from the ambient temperature (T_Ain °C) and power dissipation (P_D in Watts) as follows: T_J = T_A + (P_D • R_θJA) where R_θJA (in °C/W) is the package thermal impedance provided in Thermal Information.

7.6 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER		TEST CONDITIONS	TYP	UNIT
T_HO-TR T_LO-TR	HO, LO rise times	V_BST – V_SW = 7 V, C_LOAD = 1 nF, 20% to 80%	7	ns
T_HO-TF T_LO-TF	HO, LO fall times	V_BST – V_SW = 7 V, C_LOAD = 1 nF, 80% to 20%	4	ns
T_HO-DT	HO turnon dead time	V_BST – V_SW = 7 V, LO off to HO on, 50% to 50%	14	ns
T_LO-DT	LO turnon dead time	V_BST – V_SW = 7 V, HO off to LO on, 50% to 50%	14	ns