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ZHCSE64C august 2015 – may 2023 ISO5452

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

DW|16

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcse64c_oa

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_r	Output signal rise time, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 1 nF	12		35	ns
t_r		C_LOAD = 1 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		18		ns
t_f	Output signal fall time, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 1 nF	12		37	ns
t_f		C_LOAD = 1 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		20		ns
t_PLH, t_PHL	Propagation delay, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 1 nF		76	110	ns
t_PLH, t_PHL		C_LOAD = 1 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V				ns
t_sk-p	Pulse skew \|t_PHL – t_PLH\|, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 1 nF			20	ns
t_sk-pp	Part-to-part skew, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 1 nF			30⁽¹⁾	ns
t_GF	Glitch filter on IN+, IN–, RST, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 1 nF	20		40	ns
t_GF		C_LOAD = 1 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		30		ns
t_{DS (90%)}	DESAT sense to 90% V_OUTH/L delay, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 10 nF			760	ns
t_{DS (90%)}		C_LOAD = 10 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		553		ns
t_{DS (10%)}	DESAT sense to 10% V_OUTH/L delay, see Figure 8-1, Figure 8-2, and Figure 8-3	C_LOAD = 10 nF			3.5	μs
t_{DS (10%)}		C_LOAD = 10 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		2		μs
t_{DS (GF)}	DESAT glitch filter delay	C_LOAD = 1 nF, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		330		ns
t_{DS ( FLT)}	DESAT sense to FLT-low delay, see Figure 8-3				1.4	μs
t_LEB	Leading edge blanking time, see Figure 8-1and Figure 8-2		310		480	ns
t_LEB	Leading edge blanking time, see Figure 8-1and Figure 8-2	T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		400		ns
t_GF(RSTFLT)	Glitch filter on RST for resetting FLT		300		800	ns
C_I	Input capacitance⁽²⁾	V_I = V_CC1 / 2 + 0.4 × sin (2πft), f = 1 MHz, V_CC1 = 5 V, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		2		pF
CMTI	Common-mode transient immunity, see Figure 8-4	V_CM = 1500 V	50			kV/μs
CMTI	Common-mode transient immunity, see Figure 8-4	V_CM = 1500 V, T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V		100		kV/μs

(1) Measured at same supply voltage and temperature condition

(2) Measured from input pin to ground.