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SNLS321C May 2010 – May 2016 DS92LV2421 , DS92LV2422

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

NKB|60
- MPQS030A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
Supply voltage, V_DDn (1.8 V)		–0.3	2.5	V
Supply voltage, V_DDIO		–0.3	4	V
LVCMOS I/O voltage		–0.3	VDDIO + 0.3	V
Receiver input voltage		–0.3	VDD + 0.3	V
Driver output voltage		–0.3	VDD + 0.3	V
48L RHS package	Maximum power dissipation capacity at 25°C		225	mW
48L RHS package	Derate above 25°C		1 / R_θJA	mW/°C
60L NKB package	Maximum power dissipation capacity at 25°C		525	mW
60L NKB package	Derate above 25°C		1 / R_θJA	mW/°C
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) For soldering specifications, see product folder at www.ti.com and SNOA549.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±8000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±1000
		Machine model (MM)		±250
		IEC 61000-4-2 contact discharge	D_OUT+, D_OUT-	≥±8000
		IEC 61000-4-2 contact discharge	R_IN+, R_IN-	≥±8000
		IEC 61000-4-2 air-gap discharge	D_OUT+, D_OUT-	≥±25000
		IEC 61000-4-2 air-gap discharge	R_IN+, R_IN-	≥±25000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_DDn	Supply voltage	1.71	1.8	1.89	V
V_DDIO	LVCMOS supply voltage	1.71	1.8	1.89	V
V_DDIO	LVCMOS supply voltage	3	3.3	3.6	V
	Clock frequency	10		75	MHz
	Supply noise⁽¹⁾			50	mV_p-p
T_A	Operating free-air temperature	–40	25	85	°C

(1) Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the V_DDn (1.8 V) supply with amplitude = 100 mV_p-p measured at the device V_DDn pins. Bit error rate testing of input to the serializer and output of the deserializer with 10 meter cable shows no error when the noise frequency on the serializer is less than 750 kHz. The deserializer, on the other hand, shows no error when the noise frequency is less than 400 kHz.

6.4 Thermal Information

Over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC⁽¹⁾		DS92LV2421	DS92LV2422	UNIT
		RHS (WQFN)	NKB (WQFN)
		48 PINS	60 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	30.3	26.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽²⁾	11.5	9.1	°C/W
R_θJB	Junction-to-board thermal resistance	7.3	6	°C/W
ψ_JT	Junction-to-top characterization parameter	0.1	0.1	°C/W
ψ_JB	Junction-to-board characterization parameter	7.3	6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.7	1.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) Based on nine thermal vias.

6.5 Electrical Characteristics – Serializer DC

Over recommended operating supply and temperature ranges (unless otherwise noted).⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
LVCMOS INPUT DC SPECIFICATIONS
V_IH	High level input voltage	V_DDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)		2.2		V_DDIO	V
V_IH	High level input voltage	V_DDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)		0.65 × V_DDIO		V_DDIO	V
V_IL	Low level input voltage	V_DDIO = 3 V to 3.6 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)		GND		0.8	V
V_IL	Low level input voltage	V_DDIO = 1.71 V to 1.89 V (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)		GND		0.35 × V_DDIO	V
I_IN	Input current	V_IN = 0 V or V_DDIO (DI[23:0], CI1,CI2,CI3, CLKIN, PDB, VODSEL, RFB, BISTEN, and CONFIG[1:0] pins)	V_DDIO = 3 V to 3.6 V	–15	±1	15	μA
I_IN	Input current		V_DDIO = 1.7 V to 1.89 V	–15	±1	15	μA
CML DRIVER DC SPECIFICATIONS
V_OD	Differential output voltage	R_L = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins)	VODSEL = 0	±205	±280	±355	mV
V_OD	Differential output voltage		VODSEL = 1	±320	±420	±520	mV
VOD_p-p	Differential output voltage (DOUT+) – (DOUT-)	R_L = 100 Ω, de-emphasis = disabled (see Figure 2; DOUT+ and DOUT– pins)	VODSEL = 0		560		mV_p-p
VOD_p-p	Differential output voltage (DOUT+) – (DOUT-)		VODSEL = 1		840		mV_p-p
ΔV_OD	Output voltage unbalance	R_L = 100 Ω, de-emphasis = disabled, VODSEL = L (DOUT+ and DOUT– pins)			1	50	mV
V_OS	Offset voltage (single-ended)	At TP A and B (see Figure 1), R_L = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins)	VODSEL = 0		1.65		V
V_OS	Offset voltage (single-ended)		VODSEL = 1		1.575		V
ΔV_OS	Offset voltage unbalance (single-ended)	At TP A and B (see Figure 1), R_L = 100 Ω, de-emphasis = disabled (DOUT+ and DOUT– pins)			1		mV
I_OS	Output short circuit current	DOUT± = 0 V, de-emphasis = disabled, VODSEL = 0 (DOUT+ and DOUT– pins)			–36		mA
R_TO	Internal output termination resistor	DOUT+ and DOUT– pins		80	100	120	Ω
SUPPLY CURRENT
I_DDT1	Serializer supply current (includes load current)	R_L = 100 Ω, CLKIN = 75 MHz, checker board pattern, de-emphasis = 3 kΩ, VODSEL = H (see Figure 9)	V_DD = 1.89 V		75	90	mA
I_DDT1			V_DDIO = 1.89 V		3	5
I_DDIOT1			V_DDIO = 3.6 V		11	15
I_DDT2	Serializer supply current (includes load current)	R_L = 100 Ω, CLKIN = 75 MHz, checker board pattern, de-emphasis = 6 kΩ, VODSEL = L (see Figure 9)	V_DD = 1.89 V		65	80	mA
I_DDT2			V_DDIO = 1.89 V		3	5
I_DDIOT2			V_DDIO = 3.6 V		11	15
I_DDZ	Serializer supply current power-down	PDB = 0 V, All other LVCMOS Inputs = 0 V	V_DD = 1.89 V		40	1000	µA
I_DDZ			V_DDIO = 1.89 V		5	10
I_DDIOZ			V_DDIO = 3.6 V		10	20

(1) The electrical characteristics tables list verified specifications under the listed recommended operating conditions except as otherwise modified or specified by the electrical characteristics conditions or notes. Typical specifications are estimations only and are not verified.

(2) Typical values represent most likely parametric norms at V_DD = 3.3 V, T_A = 25°C, and at the recommended operation conditions at the time of product characterization and are not verified.

(3) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except V_OD, ΔV_OD, V_TH, and V_TL, which are differential voltages.

6.6 Electrical Characteristics – Deserializer DC

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
3.3-V I/O LVCMOS DC SPECIFICATIONS (V_DDIO = 3 V TO 3.6 V)
V_IH	High level input voltage	PDB and BISTEN pins		2.2		V_DDIO	V
V_IL	Low level input voltage	PDB and BISTEN pins		GND		0.8	V
I_IN	Input current	V_IN = 0 V or V_DDIO (PDB and BISTEN pins)		−15	±1	15	μA
V_OH	High level output voltage	I_OH = −2 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins)		2.4	V_DDIO		V
V_OL	Low level output voltage	I_OL = 3 mA, OS_CLKOUT/DATA = L (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins)			GND	0.4	V
I_OS	Output short circuit current	V_DDIO = 3.3 V, V_OUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin)			36		mA
I_OS	Output short circuit current	V_DDIO = 3.3 V, V_OUT = 0 V, OS_CLKOUT/DATA = L/H (output pins)			37		mA
I_OZ	TRI-STATE output current	PDB = 0 V, OSS_SEL = 0 V, V_OUT = H (output pins)		−15		15	µA
1.8-V I/O LVCMOS DC SPECIFICATIONS (V_DDIO = 1.71 V to 1.89 V)
V_IH	High level input voltage	PDB and BISTEN pins		1.235		V_DDIO	V
V_IL	Low level input voltage	PDB and BISTEN pins		GND		0.595	V
I_IN	Input current	V_IN = 0 V or V_DDIO (PDB and BISTEN pins)		−15	±1	15	μA
V_OH	High level output voltage	I_OH = –2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins)		V_DDIO – 0.45	V_DDIO		V
V_OL	Low level output voltage	I_OL = 2 mA, OS_CLKOUT/DATA = L/H (DO[23:0], CO1, CO2, CO3, CLKOUT, LOCK, and PASS pins)		GND		0.45	V
I_OS	Output short circuit current	V_DDIO = 1.8 V, V_OUT = 0 V, OS_CLKOUT/DATA = L/H (CLKOUT pin)			18		mA
I_OS	Output short circuit current	V_DDIO = 1.8 V, V_OUT = 0 V, OS_CLKOUT/DATA = L/H (output pins)			18		mA
I_OZ	TRI-STATE output current	PDB = 0 V, OSS_SEL = 0 V, V_OUT = 0 V or V_DDIO (output pins)		–15		15	µA
CML RECEIVER DC SPECIFICATIONS
V_TH	Differential input threshold high voltage	V_CM = 1.2 V, RIN+ and RIN- pins (Internal V_BIAS)		50			mV
V_TL	Differential input threshold low voltage	V_CM = 1.2 V, RIN+ and RIN- pins (Internal V_BIAS)		–50			mV
V_CM	Common mode voltage	RIN+ and RIN- pins (Internal V_BIAS)			1.2		V
I_IN	Input current	V_IN = 0 V or V_DDIO, RIN+ and RIN- pins		–15		15	µA
R_TI	Internal input termination resistor	RIN+ and RIN- pins		80	100	120	Ω
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS (EQ TEST PORT⁽¹⁾)
V_OD	Differential output voltage	ROUT+ and ROUT- pins, R_L = 100 Ω			542		mV
V_OS	Offset voltage (single-ended)	ROUT+ and ROUT- pins, R_L = 100 Ω			1.4		V
R_T	Internal termination resistor	ROUT+ and ROUT- pins		80	100	120	Ω
SUPPLY CURRENT
I_DD1	Deserializer supply current (includes load current)	CLKOUT = 75 MHz, checker board pattern, OS_CLKOUT/DATA = H, C_L = 4 pF (see Figure 9)	V_DD = 1.89 V		97	115	mA
I_DDIO1			V_DDIO = 1.89 V		40	50
I_DDIO1			V_DDIO = 3.6 V		75	85
I_DDZ	Deserializer supply current power down	PDB = 0 V, All other LVCMOS Inputs = 0 V	V_DD = 1.89 V		100	3000	µA
I_DDZ			V_DDIO = 1.89 V		6	50
I_DDIOZ			V_DDIO = 3.6 V		12	100

(1) Specification is verified by characterization and is not tested in production.

6.7 Electrical Characteristics – DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Input high level	SDA and SCL	2.2		V_DDIO	V
V_IL	Input low level voltage	SDA and SCL	GND		0.8	V
V_HY	Input hysteresis			>50		mV
V_OL	Output low level voltage⁽¹⁾	SDA, I_OL = 1.25 mA, V_DDIO = 3.3 V	0		0.4	V
I_in	Input current	SDA or SCL, Vin = V_DDIO or GND	–15		15	µA
C_in	Input capacitance	SDA or SCL		<5		pF

(1) Specification is verified by characterization and is not tested in production.

6.8 Timing Requirements – DC and AC Serial Control Bus

Over 3.3-V supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS	TYP	UNIT
t_R	SDA rise time (read)	SDA, RPU = 10 kΩ, Cb ≤ 400 pF	40	ns
t_F	SDA fall time (read)	SDA, RPU = 10 kΩ, Cb ≤ 400 pF	25	ns
t_SU;DAT	Set up time (read)		520	ns
t_HD;DAT	Hold up time (read)		55	ns
t_SP	Input filter		50	ns

6.9 Timing Requirements – Serializer for CLKIN

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
t_TCP	Transmit input CLKIN period	10 MHz to 75 MHz (see Figure 4)	13.3	T	100	ns
t_TCIH	Transmit input CLKIN high time	10 MHz to 75 MHz (see Figure 4)	0.4 × T	0.5 × T	0.6 × T	ns
t_TCIL	Transmit input CLKIN low time	10 MHz to 75 MHz (see Figure 4)	0.4 × T	0.5 × T	0.6 × T	ns
t_CLKT	CLKIN input transition time	10 MHz to 75 MHz (see Figure 4)	0.5		2.4	ns
SSC_IN	CLKIN input	fmod (spread spectrum at 75 MHz)			35	kHz
SSC_IN	CLKIN input	fdev (spread spectrum at 75 MHz)			±2%

6.10 Timing Requirements – Serial Control Bus

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
f_SCL	SCL clock frequency	Standard mode		100	kHz
f_SCL	SCL clock frequency	Fast mode		400	kHz
t_LOW	SCL low period	Standard mode	4.7		μs
t_LOW	SCL low period	Fast mode	1.3		μs
t_HIGH	SCL high period	Standard mode	4		μs
t_HIGH	SCL high period	Fast mode	0.6		μs
t_HD;STA	Hold time for a start or a repeated start condition (see Figure 18)	Standard mode	4		μs
t_HD;STA		Fast mode	0.6		μs
t_SU:STA	Set up time for a start or a repeated start condition (see Figure 18)	Standard mode	4.7		μs
t_SU:STA		Fast mode	0.6		μs
t_HD;DAT	Data hold time (see Figure 18)	Standard mode	0	3.45	μs
t_HD;DAT	Data hold time (see Figure 18)	Fast mode	0	0.9	μs
t_SU;DAT	Data set up time (see Figure 18)	Standard mode	250		ns
t_SU;DAT	Data set up time (see Figure 18)	Fast mode	100		ns
t_SU;STO	Set up time for STOP condition (see Figure 18)	Standard mode	4		μs
t_SU;STO	Set up time for STOP condition (see Figure 18)	Fast mode	0.6		μs
t_BUF	Bus free time (between STOP and START; see Figure 18)	Standard mode	4.7		μs
t_BUF	Bus free time (between STOP and START; see Figure 18)	Fast mode	1.3		μs
t_r	SCL and SDA rise time (see Figure 18)	Standard mode		1000	ns
t_r	SCL and SDA rise time (see Figure 18)	Fast mode		300	ns
t_f	SCL and SDA fall time (see Figure 18)	Standard mode		300	ns
t_f	SCL and SDA fall time (see Figure 18)	Fast mode		300	ns

6.11 Switching Characteristics – Serializer

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_LHT	Serializer output low-to-high transition time (see Figure 3)	R_L = 100 Ω, de-emphasis = disabled, VODSEL = 0		200		ps
t_LHT		R_L = 100 Ω, de-emphasis = disabled, VODSEL = 1		200		ps
t_HLT	Serializer output high-to-low transition time (see Figure 3)	R_L = 100 Ω, de-emphasis = disabled, VODSEL = 0		200		ps
t_HLT		R_L = 100 Ω, de-emphasis = disabled, VODSEL = 1		200		ps
t_DIS	Input data, setup time (see Figure 4)	DI[23:0], CI1, CI2, CI3 to CLKIN	2			ns
t_DIH	Input data, hold time (see Figure 4)	CLKIN to DI[23:0], CI1, CI2, CI3	2			ns
t_XZD	Serializer output active to OFF delay (see Figure 6)⁽¹⁾			8	15	ns
t_PLD	Serializer PLL lock time (see Figure 5)⁽¹⁾⁽²⁾⁽³⁾	R_L = 100 Ω		1.4	10	ms
t_SD	Serializer delay, latency (see Figure 7)⁽¹⁾	R_L = 100 Ω		144 × T	145 × T	ns
t_DJIT	Serializer output total jitter (see Figure 8)	R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz		0.28		UI⁽⁴⁾
		R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz		0.27
		R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz		0.35
λ_STXBW	Serializer jitter transfer (function –3 dB bandwidth)	R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz		3.3		MHz
		R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz		2.3
		R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz		0.8
δ_STX	Serializer jitter transfer (function peaking)	R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 75 MHz		0.86		dB
		R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 43 MHz		0.83
		R_L = 100 Ω, de-emphasis = disabled, RANDOM pattern, CLKIN = 10 MHz		0.28

(1) Specification is verified by characterization and is not tested in production.

(2) t_PLD and t_DDLT is the time required by the serializer and deserializer, respectively, to obtain lock when exiting power-down state with an active clock.

(3) When the serializer output is at TRI-STATE the Deserializer loses PLL lock. Resynchronization and Re-lock must occur before data transfer require t_PLD

(4) UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 x CLK]). The UI scales with clock frequency.

6.12 Switching Characteristics – Deserializer

Over recommended operating supply and temperature ranges (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_RCP	CLK output period	t_RCP = t_TCP (CLKOUT)		13.3	T	100	ns
t_RDC	CLK output duty cycle	CLKOUT	SSCG = OFF, 10 to 75 MHz	40%	50%	60%
			SSCG = ON, 10 to 20 MHz	35%	59%	65%
			SSCG = ON, 10 to 65 MHz	40%	53%	60%
t_CLH	LVCMOS low-to-high transition time (see Figure 10)	DO[23:0], CO1, CO2, CO3	V_DDIO = 1.8 V, C_L = 4 pF, OS_CLKOUT/DATA = L		2.1		ns
t_CLH	LVCMOS low-to-high transition time (see Figure 10)	DO[23:0], CO1, CO2, CO3	V_DDIO = 3.3 V, C_L = 4 pF, OS_CLKOUT/DATA = H		2		ns
t_CHL	LVCMOS high-to-low transition time (see Figure 10)	DO[23:0], CO1, CO2, CO3	V_DDIO = 1.8 V, C_L = 4 pF, OS_CLKOUT/DATA = L		1.6		ns
t_CHL	LVCMOS high-to-low transition time (see Figure 10)	DO[23:0], CO1, CO2, CO3	V_DDIO = 3.3 V, C_L = 4 pF, OS_CLKOUT/DATA = H		1.5		ns
t_ROS	Data valid before CLKOUT, setup time (see Figure 14)	V_DDIO = 1.71 to 1.89 V or 3 to 3.6 V, C_L = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3		0.23 × T	0.5 × T		ns
t_ROH	Data valid after CLKOUT, hold time (see Figure 14)	V_DDIO = 1.71 to 1.89 V or 3 to 3.6 V, C_L = 4 pF (lumped load), DO[23:0], CO1, CO2, CO3		0.33 × T	0.5 × T		ns
t_DDLT	Deserializer lock time (see Figure 13)	CLKOUT = 10 MHz, SSC[3:0] = OFF⁽¹⁾			3		ms
		CLKOUT = 75 MHz, SSC[3:0] = OFF⁽¹⁾			4
		CLKOUT = 10 MHz, SSC[3:0] = ON⁽¹⁾			30
		CLKOUT = 65 MHz, SSC[3:0] = ON⁽¹⁾			6
t_DD	Deserializer delay, latency (see Figure 11)	CLKOUT = 10 to 75 MHz, SSC[3:0] = OFF⁽²⁾			139 × T	140 × T	ns
t_DPJ	Deserializer period jitter	SSC[3:0] = OFF⁽³⁾⁽²⁾	CLKOUT = 10 MHz		500	1000	ps
			CLKOUT = 65 MHz		550	1250
			CLKOUT = 75 MHz		435	900
t_DCCJ	Deserializer cycle-to-cycle jitter	SSC[3:0] = OFF⁽⁴⁾⁽²⁾⁽⁵⁾	CLKOUT = 10 MHz		375	900	ps
			CLKOUT = 65 MHz		500	1150
			CLKOUT = 75 MHz		460	1000
t_IJT	Deserializer input jitter tolerance (see Figure 16)	EQ = OFF, SSCG = OFF, CLKOUT = 75 MHz	jitter freq < 2 MHz		0.9		UI⁽⁶⁾
t_IJT	Deserializer input jitter tolerance (see Figure 16)	EQ = OFF, SSCG = OFF, CLKOUT = 75 MHz	jitter freq > 6 MHz		0.5		UI⁽⁶⁾
BIST MODE
t_PASS	BIST PASS valid time (see Figure 17)	BISTEN = 1			1	10	μs
SSCG MODE
f_DEV	Spread spectrum clocking deviation frequency	CLKOUT = 10 to 65 MHz, SSC[3:0] = ON		±0.5%		±2%
f_MOD	Spread spectrum clocking modulation frequency	CLKOUT = 10 to 65 MHz, SSC[3:0] = ON		8		100	kHz

(1) t_PLD and t_DDLT is the time required by the serializer and deserializer, respectively, to obtain lock when exiting power-down state with an active clock.

(2) Specification is verified by design and is not tested in production.

(3) t_DPJ is the maximum amount the period is allowed to deviate over many samples.

(4) Specification is verified by characterization and is not tested in production.

(5) t_DCCJ is the maximum amount of jitter between adjacent clock cycles.

(6) UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 x CLK]). The UI scales with clock frequency.