ZHCSMR4A november 2020 – november 2020 DS90UB662-Q1
PRODUCTION DATA
The DS90UB662-Q1 can detect and measure the approximate input frequency and frequency stability of each RX input port and indicate status in bits [2:1] of RX_PORT_STS2 (see Table 7-92). Frequency measurement stable FREQ_STABLE indicates the FPD-Link III input clock frequency is stable. When no FPD-Link III input clock is detected at the RX input port, the NO_FPD3_CLK bit indicates that condition has occurred. The setting of these error flags is dependent on the stability control settings in the FREQ_DET_CTL register 0x77 (see Table 7-133). The NO_FPD3_CLK bit will be set if the input frequency is below the setting programmed in the FREQ_LO_THR setting in the FREQ_DET_CTL register. A change in frequency FREQ_STABLE = 0, is defined as any change in MHz greater than the value programmed in the FREQ_HYST value. The frequency is continually monitored and provided for readback through the I2C interface less than every 1 ms. A 16-bit value is used to provide the frequency in registers 0x4F and 0x50 (see Table 7-93 and Table 7-94). An interrupt can also be generated for any of the ports to indicate if a change in frequency is detected on any port.