ZHCSC07E December   2013  – March 2019

PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用范圍
3. 3 說(shuō)明
4. 4 修訂歷史記錄
5. 5 Pin Configuration and Functions
   1.     Pin Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  Typical Current and Power Dissipation
   6. 6.6  I/O Characteristics
   7. 6.7  Internal Pullup and Pulldown Characteristics
   8. 6.8  Parallel I/F Frame Timing Requirements
   9. 6.9  Parallel I/F General Timing Requirements
   10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
   11. 6.11 BT.656 I/F General Timing Requirements
   12. 6.12 100- to 120-Hz Operational Limitations
   13. 6.13 Flash Interface Timing Requirements
   14. 6.14 DMD Interface Timing Requirements
   15. 6.15 mDDR Memory Interface Timing Requirements
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
   4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
         1. 8.2.2.1 Reference Clock
         2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
         1. 8.2.3.1 Hot-Plug Usage
         2. 8.2.3.2 Maximum Signal Transition Time
         3. 8.2.3.3 Configuration Control
         4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
9. 9 Power Supply Recommendations
   1. 9.1 System Power Considerations
   2. 9.2 System Power-Up and Power-Down Sequence
   3. 9.3 System Power I/O State Considerations
   4. 9.4 Power-Up Initialization Sequence
   5. 9.5 Power-Good (PARK) Support
10. 10Layout
    1. 10.1 Layout Guidelines
       1. 10.1.1  Internal ASIC PLL Power
       2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
       3. 10.1.3  SPI Signal Routing
       4. 10.1.4  mDDR Memory and DMD Interface Considerations
       5. 10.1.5  PCB Design
       6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
       7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
       8. 10.1.8  I/F Specific PCB Routing
       9. 10.1.9  Number of Layer Changes
       10. 10.1.10 Stubs
       11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
11. 11器件和文檔支持
    1. 11.1 器件支持
       1. 11.1.1 第三方產(chǎn)品免責(zé)聲明
       2. 11.1.2 器件命名規(guī)則
          1. 11.1.2.1 器件標(biāo)記
    2. 11.2 社區(qū)資源
    3. 11.3 商標(biāo)
    4. 11.4 靜電放電警告
    5. 11.5 術(shù)語(yǔ)表
12. 12機(jī)械、封裝和可訂購(gòu)信息
    1. 12.1 封裝選項(xiàng)附錄
       1. 12.1.1 封裝信息