SCAS793G June 2005 – August 2017 CDCM7005
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3 Feature Description
- 9.4 Device Functional Modes
- 9.5 Programming
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
- ZVA|64
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGZ|48
訂購信息
8 Parameter Measurement Information
Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time
A. Output skew, tsk(o), is calculated as the greater of:
The difference between the fastest and the slowest tpd(LH)n (n = 0...4)
The difference between the fastest and the slowest tpd(HL)n (n = 0...4)
The difference between the fastest and the slowest tpd(LH)n (n = 0...4)
The difference between the fastest and the slowest tpd(HL)n (n = 0...4)
B. Pluse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL)) and the low-to-high (tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch,
tsk(p) = |tpd(HL) – tpd(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew.
Figure 10. Output Skew
tsk(p) = |tpd(HL) – tpd(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew.
Figure 11. Phase Offset
Figure 12. LVCMOS Output Loading During Device Test
Figure 13. LVPECL Output Loading During Device Test