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SCAS880F August 2009 – September 2015 CDCLVP1204

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGT|16
- MPQF119H

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGT|16
- QFND097Q

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
V_CC	Supply voltage range⁽²⁾	–0.5	4.6	V
V_IN	Input voltage range⁽³⁾	–0.5	V_CC + 0.5	V
V_OUT	Output voltage range⁽³⁾	–0.5	V_CC + 0.5	V
I_IN	Input current		20	mA
I_OUT	Output current		50	mA
T_A	Specified free-air temperature range (no airflow)	–40	85	°C
T_J	Maximum junction temperature		125	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability..

(2) All supply voltages must be supplied simultaneously.

(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted).

		MIN	NOM	MAX	UNIT
V_CC	Supply voltage	2.375	2.50/3.30	3.60	V
T_A	Ambient temperature	–40		85	°C
T_PCB	PCB temperature (measured at thermal pad)			105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽³⁾⁽⁴⁾		CDCLVP1204	UNIT
		RGT (QFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	51.8, 0 LFM⁽²⁾	°C/W
		22.6, 150 LFM⁽²⁾
		19.2, 400 LFM⁽²⁾
R_θJC(top)	Junction-to-case (top) thermal resistance	79	°C/W
R_θ_JP⁽⁵⁾	Junction-to-pad thermal resistance	6.12⁽²⁾	°C/W
ψ_JT	Junction-to-top characterization parameter	1.4	°C/W
ψ_JB	Junction-to-board characterization parameter	19	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	6.12	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) 2 x 2 vias on Pad

(3) The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).

(4) Connected to GND with four thermal vias (0.3-mm diameter).

(5) R_θJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN package.

6.5 Terminal Characteristics

PARAMETER		MIN	TYP	MAX	UNIT
R_PULLDOWN	Input pulldown resistor		150		kΩ

6.6 Electrical Characteristics: LVCMOS Input

At V_CC = 2.375 V to 3.6 V and T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted).⁽¹⁾

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency				200	MHz
V_th	Input threshold voltage	External threshold voltage applied to complementary input	1.1		1.8	V
V_IH	Input high voltage		V_th + 0.1		V_CC	V
V_IL	Input low voltage		0		V_th – 0.1	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
Δ_V/Δ_T	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 6 and Figure 7 show DC test setup.

6.7 Electrical Characteristics: Differential Input

At V_CC = 2.375 V to 3.6 V and T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted). ⁽¹⁾

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_IN	Input frequency	Clock input			2000	MHz
V_{IN, DIFF, PP}	Differential input peak-peak voltage	f_IN ≤ 1.5 GHz	0.1		1.5	V
V_{IN, DIFF, PP}	Differential input peak-peak voltage	1.5 GHz ≤ f_IN ≤ 2 GHz	0.2		1.5	V
V_ICM	Input common-mode level		1		V_CC – 0.3	V
I_IH	Input high current	V_CC= 3.6 V, V_IH = 3.6 V			40	μA
I_IL	Input low current	V_CC= 3.6 V, V_IL = 0 V			–40	μA
ΔV/ΔT	Input edge rate	20% to 80%	1.5			V/ns
I_CAP	Input capacitance			5		pF

(1) Figure 5 and Figure 8 show DC test setup. Figure 9 shows AC test setup.

6.8 Electrical Characteristics: LVPECL Output

V_CC = 2.375 V to 2.625 V; T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted).⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85ºC	V_CC – 1.26		V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤ 105ºC	V_CC – 1.26		V_CC – 0.83	V
V_OL	Output low voltage	T_A ≤ 85ºC	V_CC – 1.7		V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤ 105ºC	V_CC – 1.7		V_CC – 1.25	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.5		1.35	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN = 125 MHz, 312.5 MHz		1.15		V
V_{AC_REF}	Input bias voltage^⁽²⁾	I_{AC_REF} = 2 mA	V_CC – 1.6		V_CC – 1.1	V
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1 V			450	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V			450	ps
t_SK,PP	Part-to-part skew				100	ps
t_SK,O	Output skew				15	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	f_OUT = 100 MHz, V_IN,SE = V_CC, V_th = 1.25 V, 10 kHz to 20 MHz		0.081		ps, RMS
		f_OUT = 100 MHz, V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.091		ps, RMS
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.041		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.088		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.081		ps, RMS
		f_OUT = 122.88 MHz,⁽⁶⁾⁽³⁾ Square Wave, V_IN-PP = 1 V, 12 kHz to 20 MHz		0.057	0.088	ps, RMS
		f_OUT = 122.88 MHz,⁽⁶⁾⁽³⁾ Square Wave, V_IN-PP = 1 V, 10 kHz to 20 MHz		0.057	0.088	ps, RMS
		f_OUT = 122.88 MHz,⁽⁶⁾⁽³⁾ Square Wave, V_IN-PP = 1 V, 1 kHz to 40 MHz		0.086	0.121	ps, RMS
		f_OUT = 156.25 MHz,⁽⁶⁾⁽⁴⁾ Square Wave, V_IN-PP = 1 V, 12 kHz to 20 MHz		0.048	0.071	ps, RMS
		f_OUT = 156.25 MHz,⁽⁶⁾⁽⁴⁾ Square Wave, V_IN-PP= 1 V, 10 kHz to 20 MHz		0.048	0.071	ps, RMS
		f_OUT = 156.25 MHz,⁽⁶⁾⁽⁴⁾ Square Wave, V_IN-PP = 1 V, 1 kHz to 40 MHz		0.068	0.097	ps, RMS
		f_OUT = 312.5 MHz,⁽⁶⁾⁽⁵⁾ Square Wave, V_IN-PP = 1 V, 12 kHz to 20 MHz		0.030	0.048	ps, RMS
		f_OUT = 312.5 MHz,⁽⁶⁾⁽⁵⁾ Square Wave, V_IN-PP = 1 V, 10 kHz to 20 MHz		0.030	0.048	ps, RMS
		f_OUT = 312.5 MHz,⁽⁶⁾⁽⁵⁾ Square Wave, V_IN-PP= 1 V, 1 kHz to 40 MHz		0.045	0.068	ps, RMS
t_R/t_F	Output rise/fall time	20% to 80%			200	ps
I_EE	Supply internal current	Outputs unterminated T_A ≤ 85ºC			45	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB ≤ 105ºC			47	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_A ≤ 85ºC			170	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_PCB ≤ 105ºC			186	mA

(1) Figure 10 and Figure 11 show DC and AC test setup.

(2) Internally generated bias voltage (V_{AC_REF}) is for 3.3 V operation only. It is recommended to apply externally generated bias voltage for V_CC < 3 V.

(3) Input source: 122.88 MHz Rohde & Schwarz SMA100A Signal Generator.

(4) Input source: 156.25 MHz Rohde & Schwarz SMA100A Signal Generator.

(5) Input source: 312.5 MHz Rohde & Schwarz SMA100A Signal Generator.

(6) Input source RMS Jitter (t_{RJIT_IN}) and Total RMS Jitter (t_{RJIT_OUT}) measured using Agilent E5052 Phase Noise Analyzer. Buffer device random additive jitter computed as: t_RJIT = SQRT[(t_{RJIT_OUT})² - (t_RJIT_{_}_IN)²].

6.9 Electrical Characteristics: LVPECL Output

V_CC = 3 V to 3.6 V; T_A = –40°C to +85°C and T_PCB ≤ 105°C (unless otherwise noted).⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_OH	Output high voltage	T_A ≤ 85ºC	V_CC – 1.26		V_CC – 0.9	V
V_OH	Output high voltage	T_PCB ≤ 105ºC	V_CC – 1.26		V_CC – 0.85	V
V_OL	Output low voltage	T_A ≤ 85ºC	V_CC – 1.7		V_CC – 1.3	V
V_OL	Output low voltage	T_PCB ≤ 105ºC	V_CC – 1.7		V_CC – 1.3	V
V_{OUT, DIFF, PP}	Differential output peak-peak voltage	f_IN ≤ 2 GHz	0.65		1.35	V
V_{AC_REF}	Input bias voltage	I_{AC_REF} = 2 mA	V_CC – 1.6		V_CC – 1.1	V
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.1 V			450	ps
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V			450	ps
t_SK,PP	Part-to-part skew				100	ps
t_SK,O	Output skew				15	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion, f_OUT = 100 MHz	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input) f_OUT = 100 MHz⁽⁶⁾	f_OUT = 100 MHz, V_IN,SE = V_CC, V_th = 1.65 V, 10 kHz to 20 MHz		0.079		ps, RMS
		f_OUT = 100 MHz, V_IN,SE = 0.9 V, V_th = 1.1 V, 10 kHz to 20 MHz		0.097		ps, RMS
		f_OUT = 2 GHz, V_IN,DIFF,PP = 0.2 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.058		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 0.15 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.094		ps, RMS
		f_OUT = 100 MHz, V_IN,DIFF,PP = 1 V, V_ICM = 1 V, 10 kHz to 20 MHz		0.088		ps, RMS
		f_OUT = 100 MHz, Input AC coupled, V_ICM = V_{AC_REF}, 12 kHz to 20 MHz		0.068		ps, RMS
	Random additive jitter (with 50% duty cycle input) f_OUT = 122.88 MHz⁽⁶⁾	f_OUT = 122.88 MHz,⁽²⁾⁽⁵⁾ Square Wave, V_IN-PP = 1 V, 12 kHz to 20 MHz		0.057		ps, RMS
		f_OUT = 122.88 MHz,⁽²⁾⁽⁵⁾ Square Wave, V_IN-PP = 1 V, 10 kHz to 20 MHz		0.057		ps, RMS
		f_OUT= 122.88 MHz,⁽²⁾⁽⁵⁾ Square Wave, V_IN-PP = 1 V, 1 kHz to 40 MHz		0.086		ps, RMS
t_RJIT	Random additive jitter (with 50% duty cycle input) f_OUT = 156.25 MHz⁽⁶⁾	f_OUT = 156.25 MHz,⁽⁵⁾⁽³⁾ Square Wave, V_IN-PP = 1 V, 12 kHz to 20 MHz		0.048		ps, RMS
		f_OUT = 156.25 MHz,⁽⁵⁾⁽³⁾ Square Wave, V_IN-PP = 1 V, 10 kHz to 20 MHz		0.048		ps, RMS
		f_OUT = 156.25 MHz,⁽⁵⁾⁽³⁾ Square Wave, V_IN-PP = 1 V, 1 kHz to 40 MHz		0.068		ps, RMS
	Random additive jitter (with 50% duty cycle input) f_OUT = 312.5 MHz⁽⁶⁾	f_OUT = 312.5 MHz,⁽⁵⁾⁽⁴⁾ Square Wave, V_IN-PP = 1 V, 12 kHz to 20 MHz		0.030		ps, RMS
		f_OUT = 312.5 MHz,⁽⁵⁾⁽⁴⁾ Square Wave, V_IN-PP = 1 V, 10 kHz to 20 MHz		0.030		ps, RMS
		f_OUT = 312.5 MHz,⁽⁵⁾⁽⁴⁾ Square Wave, V_IN-PP = 1 V, 1 kHz to 40 MHz		0.045		ps, RMS
t_R/t_F	Output rise/fall time	20% to 80%			200	ps
I_EE	Supply internal current	Outputs unterminated T_A ≤ 85ºC			45	mA
I_EE	Supply internal current	Outputs unterminated, T_PCB ≤ 105ºC			47	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_A ≤ 85ºC			170	mA
I_CC	Output and internal supply current	All outputs terminated, 50 Ω to V_CC – 2 T_PCB ≤ 105ºC			186	mA

(1) Figure 10 and Figure 11 show DC and AC test setup.

(2) Input source: 122.88 MHz Rohde & Schwarz SMA100A Signal Generator.

(3) Input source: 156.25 MHz Rohde & Schwarz SMA100A Signal Generator.

(4) Input source: 312.5 MHz Rohde & Schwarz SMA100A Signal Generator.

(5) Input source RMS Jitter (t_{RJIT_IN}) and Total RMS Jitter (t_{RJIT_OUT}) measured using Agilent E5052 Phase Noise Analyzer. Buffer device random additive jitter computed as: t_RJIT = SQRT[(t_{RJIT_OUT})² – (t_RJIT_{_IN})²].

(6) Parameter is specified by characterization. Not tested in production.

6.10 Timing Diagrams

Figure 1. Output Voltage and Rise/Fall Time

1. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn (n = 0, 1, 2....11), or as the difference between the fastest and the slowest t_PHLn (n = 0, 1, 2....11).

2. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest t_PLHn (n = 0, 1, 2....11) across multiple devices, or the difference between the fastest and the slowest t_PHLn (n = 0, 1, 2....11) across multiple devices.

Figure 2. Output and Part-To-Part Skew

6.11 Typical Characteristics

At T_A = –40°C to +85°C (unless otherwise noted).

CDCLVP1204 tc_fqcy_diff_vout_swing01_cas880.gif

Figure 3. Differential Output Peak-To-Peak Voltage Vs Frequency

CDCLVP1204 tc_fqcy_diff_vout_swing02_cas880.gif

Figure 4. Differential Output Peak-To-Peak Voltage Vs Frequency