SCAS859F January 2009 – June 2015 CDCLVP111
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Applications and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RHB|32
訂購(gòu)信息
9 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCLVP111 is a low-additive jitter LVPECL fanout buffer that can generate 5 copies of 2 selectable LVDS, CML or SSTL inputs. The CDCLVP111 can accept reference clock frequencies up to 3.5 GHz while providing low-output skew.
9.2 Typical Application
9.2.1 Fanout Buffer for Line Card Application
Figure 7. CDCLVP111 Block Diagram
9.2.1.1 Design Requirements
The CDCLVP111 shown in Figure 7 is configured to be able to select 2 inputs, a 156.25-MHz LVPECL clock from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out to desired devices, as shown.
The configuration example is driving 4 LVPECL receivers in a line card application with the following properties:
- The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP111 will need to be provided with 86-Ω emitter resistors near the driver for proper operation.
- The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP111. This ASIC features internal termination so no additional components are needed.
- The FPGA requires external AC coupling but has internal termination. Again, 86-Ω emitter resistors are placed near the CDCLVP111 and a 0.1-uF are placed to provide AC coupling. Similarly, the CPU is internally terminated and requires external AC coupling capacitors.
9.2.1.2 Detailed Design Procedure
Unused outputs can be left floating.
In this example, the PHY, ASIC, and FPGA/CPU require different schemes. Power-supply filtering and bypassing is critical for low-noise applications.
See Figure 18 for recommended filtering techniques.
9.2.1.2.1 LVPECL Output Termination
Refer to Figure 8 for output termination schemes depending on the receiver application.
Figure 8. LVPECL Output DC and AC Termination for VCC = 2.5 V
Figure 9. LVPECL Output DC and AC Termination for VCC = 3.3 V
9.2.1.2.2 Input Termination
The CDCLVP111 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 10 illustrates how to DC couple an LVCMOS input to the CDCLVP111. The series resistance (RS) should be placed close to the LVCMOS driver; the value is calculated as the difference between the transmission line impedance and the driver output impedance.
Refer to Figure 10 for proper input terminations, dependent on single ended or differential inputs.
Figure 10. DC-Coupled LVCMOS Input to CDCLVP111
Figure 11 shows how to DC couple LVDS inputs to the CDCLVP111. Figure 12 and Figure 13 describe the method of DC coupling LVPECL inputs to the CDCLVP111 for VCC = 2.5 V and VCC = 3.3 V, respectively.
Figure 11. DC-Coupled LVDS Inputs to CDCLVP111
Figure 13. DC-Coupled LVPECL Inputs to CDCLVP111 (VCC = 3.3 V)
Figure 14 and Figure 15 show the technique of AC coupling differential inputs to the CDCLVP111 for VCC = 2.5 V and VCC = 3.3 V, respectively. TI recommends to place all resistive components close to either the driver end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.
Figure 14. AC-Coupled Differential Inputs to CDCLVP111 (VCC = 2.5 V)
Figure 15. AC-Coupled Differential Inputs to CDCLVP111 (VCC = 3.3 V)
9.2.1.3 Application Curves
The CDCLVP111 low-additive noise can be shown in this line card application. The low-noise, 156.25-MHz signal with 53-fs RMS jitter drives the CDCLVP111, resulting in 86-fs RMS when integrated from 10 kHz to 20 MHz. The resultant-additive jitter is a low 68-fs RMS for this configuration.
| Reference signal is low noise signal generator | ||
(10 kHz to 20 MHz)
(10 kHz to 20 MHz)