SCAS884D August 2009 – December 2015 CDCLVP1102
PRODUCTION DATA.
This section describes the function of each block for the CDCLVP1102. Figure 3 through Figure 9 illustrate how the device should be setup for a variety of test configurations.
Figure 3. DC-Coupled LVCMOS Input During Device Test
Figure 4. Vth Variation Over LVCMOS Levels
Figure 5. DC-Coupled LVPECL Input During Device Test
Figure 6. DC-Coupled LVDS Input During Device Test
Figure 7. AC-Coupled Differential Input to Device
Figure 8. LVPECL Output DC Configuration During Device Test
Figure 9. LVPECL Output AC Configuration During Device Test
Figure 10 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 11.
Figure 10. Output Voltage and Rise/Fall Time