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SCAS901D September 2010 – November 2017 CDCLVD1212

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RHA|40
- MPQF135D

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, V_CC	–0.3	2.8	V
Input voltage, V_I	–0.2	V_CC + 0.2	V
Output voltage, V_O	–0.2	V_CC + 0.2	V
Driver short-circuit current, I_OSD	See⁽²⁾
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The output can handle the permanent short.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	>3000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	>1000	V

(1) Human-body model, 1.5-kΩ, 100-pF

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Device supply voltage	2.375	2.5	2.625	V
T_A	Ambient temperature	–40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		CDCLVD1212	UNIT
		RHA (VQFN)
		40 PINS
R_θJA	Junction-to-ambient thermal resistance	31.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	28.7	°C/W
R_θJB	Junction-to-board thermal resistance	9.3	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	9.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

V_CC = 2.375 V to 2.625 V and T_A = –40°C to 85°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
IN_SEL CONTROL INPUT CHARACTERISTICS
V_dI3	3-state input	Open		0.5 × V_CC		V
V_dIH	Input high voltage		0.7 × V_CC			V
V_dIL	Input low voltage				0.2 × V_CC	V
I_dIH	Input high current	V_CC = 2.625 V, V_IH = 2.625 V			30	μA
I_dIL	Input low current	V_CC = 2.625 V, V_IL = 0 V			–30	μA
R_{pull(IN_SEL)}	Input pullup or pulldown resistor			200		kΩ
2.5V LVCMOS (SEE Figure 5) INPUT CHARACTERISTICS
f_IN	Input frequency				200	MHz
V_th	Input threshold voltage	External threshold voltage applied to complementary input	1.1		1.5	V
V_IH	Input high voltage		V_th + 0.1		V_CC	V
V_IL	Input low voltage		0		V_th – 0.1	V
I_IH	Input high current	V_CC = 2.625 V, V_IH = 2.625 V			10	μA
I_IL	Input low current	V_CC = 2.625 V, V_IL = 0 V			–10	μA
ΔV/ΔT	Input edge rate	20%–80%	1.5			V/ns
C_IN	Input capacitance			2.5		pF
DIFFERENTIAL INPUT CHARACTERISTICS
f_IN	Input frequency	Clock input			800	MHz
V_{IN, DIFF}	Differential input voltage peak-to-peak	V_ICM = 1.25 V	0.3		1.6	V_PP
V_ICM	Input common-mode voltage range	V_{IN, DIFF, PP} > 0.4 V	1		V_CC – 0.3	V
I_IH	Input high current	V_CC = 2.625 V, V_IH = 2.625 V			10	μA
I_IL	Input low current	V_CC = 2.625, V_IL = 0 V			–10	μA
ΔV/ΔT	Input edge rate	20%–80%	0.75			V/ns
C_IN	Input capacitance			2.5		pF
LVDS OUTPUT CHARACTERISTICS
\|V_OD\|	Differential output voltage magnitude	V_{IN, DIFF, PP} = 0.3 V, R_L = 100 Ω	250		450	mV
ΔV_OD	Change in differential output voltage magnitude		–15		15	mV
V_OC(SS)	Steady-state common-mode output voltage		1.1		1.375	V
ΔV_OC(SS)	Steady-state common-mode output voltage	V_{IN, DIFF, PP} = 0.6 V, R_L = 100 Ω	–15		15	mV
V_ring	Output overshoot and undershoot	Percentage of output amplitude V_OD			10%
V_OS	Output AC common mode	V_{IN, DIFF, PP} = 0.6 V, R_L = 100 Ω		40	70	mV_PP
I_OS	Short-circuit output current	V_OD = 0 V			±24	mA
t_PD	Propagation delay	V_{IN, DIFF, PP} = 0.3 V		1.5	2.5	ns
t_{SK, PP}	Part-to-part skew				600	ps
t_{SK, O}	Output skew				35	ps
t_SK,P	Pulse skew (with 50% duty cycle input)	Crossing-point-to-crossing-point distortion	–50		50	ps
t_RJIT	Random additive jitter (with 50% duty cycle input)	Edge speed 0.75 V/ns, 10 kHz – 20 MHz			0.3	ps, RMS
t_R/t_F	Output rise/fall time	20% to 80%, 100 Ω, 5 pF	50		300	ps
I_CCSTAT	Static supply current	Outputs unterminated, f = 0 Hz		17	28	mA
I_CC100	Supply current	All outputs, R_L = 100 Ω, f = 100 MHz		85	110	mA
I_CC800	Supply current	All outputs, R_L = 100 Ω, f = 800 MHz		117	146	mA
V_{AC_REF} CHARACTERISTICS
V_{AC_REF}	Reference output voltage	V_CC = 2.5 V, I_load = 100 µA	1.1	1.25	1.35	V

6.6 Timing Requirements

		NOM	UNIT
ADDITIVE PHASE NOISE FOR 100-MHZ CLOCK
phn₁₀₀	Phase noise at 100-Hz offset	–132.9	dBc/Hz
phn_1k	Phase noise at 1-kHz offset	–138.8	dBc/Hz
phn_10k	Phase noise at 10-kHz offset	–147.4	dBc/Hz
phn_100k	Phase noise at 100-kHz offset	–153.6	dBc/Hz
phn_1M	Phase noise at 1-MHz offset	–155.2	dBc/Hz
phn_10M	Phase noise at 10-MHz offset	–156.2	dBc/Hz
phn_20M	Phase noise at 20-MHz offset	–156.6	dBc/Hz
t_RJIT	Random additive jitter from 10 kHz to 20 MHz	171	fs, RMS
ADDITIVE PHASE NOISE FOR 737.27-MHZ CLOCK
phn₁₀₀	Phase noise at 100-Hz offset	–80.2	dBc/Hz
phn_1k	Phase noise at 1-kHz offset	–114.3	dBc/Hz
phn_10k	Phase noise at 10-kHz offset	–138	dBc/Hz
phn_100k	Phase noise at 100-kHz offset	–143.9	dBc/Hz
phn_1M	Phase noise at 1-MHz offset	–145.2	dBc/Hz
phn_10M	Phase noise at 10-MHz offset	–146.5	dBc/Hz
phn_20M	Phase noise at 20-MHz offset	–146.6	dBc/Hz
t_RJIT	Random additive jitter from 10 kHz to 20 MHz	65	fs, RMS

6.7 Typical Characteristics

Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs, T_A = 25°C, and V_CC = 2.5 V

Figure 1. 100-MHz Input and Output Phase Noise Plot

Figure 2. Differential Output Voltage vs Frequency