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SCAS841D February 2007 – December 2016 CDCLVD110A

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

VF|32
- MTQF002C
RHB|32
- MPQF130D

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- QFND722

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
Supply voltage, V_DD	–0.3	2.8	V
Input voltage, V_I	–0.2	V_DD + 0.2	V
VI output voltage, V_O	–0.2	V_DD + 0.2	V
Driver short-circuit current, I_OSD (Qn, Qn)	Continuous
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽³⁾	2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) HBM 1.5-kΩ, 100-pF

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	Supply voltage	2.375	2.5	2.625	V
V_IC	Receiver common-mode input voltage	0.5 × \|V_ID\|		V_DD – 0.5 × \|V_ID\|	V
T_A	Operating free-air temperature	–40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		CDCLVD110A		UNIT
		VF (LQFN)	RHB (VQFN)
		32 PINS	32 PINS
R_θJA	Junction-to-ambient thermal resistance	85.1	45.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	23.3	37.5	°C/W
R_θJB	Junction-to-board thermal resistance	49.4	17.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.9	1.5	°C/W
ψ_JB	Junction-to-board characterization parameter	48.7	17.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	9.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DRIVER
\|V_OD\|	Differential output voltage	R_L = 100 Ω	250	450	600	mV
ΔV_OD	V_OD magnitude change				50	mV
V_OS	Offset voltage	–40°C to 85°C	0.95	1.2	1.45	V
ΔV_OS	V_OS magnitude change				350	mV
I_OS	Output short-circuit current	V_O = 0 V			–20	mA
I_OS	Output short-circuit current	\|V_OD\| = 0 V			20	mA
V_BB	Reference output voltage	V_DD = 2.5 V, I_BB = –100 µA	1.15	1.25	1.35	V
C_O	Output capacitance	V_O = V_DD or GND		3		pF
RECEIVER
V_IDH	Input threshold high				100	mV
V_IDL	Input threshold low		–100			mV
\|V_ID\|	Input differential voltage		200			mV
I_IH	Input current, CLK0/CLK0	V_I = V_DD	–5		5	µA
I_IL	Input current, CLK1/CLK1	V_I = 0 V	–5		5	µA
C_I	Input capacitance	V_I = V_DD or GND		3		pF
SUPPLY CURRENT
I_DD	Supply current, full loaded and no load	All outputs enabled and loaded, R_L = 100 Ω, f = 100 MHz		100	110	mA
		All outputs enabled and loaded, R_L = 100 Ω, f = 800 MHz		150	160
		Outputs enabled, no output load, f = 0 Hz			35
I_DDZ	Supply current, 3-state	All outputs 3-state by control logic, f = 0 Hz			35	mA

6.6 Switching Characteristics: LVDS

over recommended operating free-air temperature range and V_DD = 2.5 V ±5% (unless otherwise noted)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	TYP	MAX	UNIT
t_PLH	Propagation delay low-to-high	CLK0, CLK0 CLK1, CLK1	Qn, Qn		2	3	ns
t_PHL	Propagation delay high-to-low	CLK0, CLK0 CLK1, CLK1	Qn, Qn		2	3	ns
t_duty	Duty cycle	CLK0, CLK0 CLK1, CLK1	Qn, Qn	45%		55%
t_sk(o)	Output skew		Any Qn, Qn		30		ps
t_sk(p)	Pulse skew		Any Qn, Qn			50	ps
t_sk(pp)	Part-to-part skew		Any Qn, Qn			600	ps
t_r	Output rise time, 20% to 80%, R_L = 100 Ω, C_L = 5 pF		Any Qn, Qn			350	ps
t_f	Output fall time, 20% to 80%, R_L = 100 Ω, C_L = 5 pF		Any Qn, Qn			350	ps
f_clk	Max input frequency	CLK0, CLK0 CLK1, CLK1	Any Qn, Qn	900	1100		MHz

6.7 Jitter Characteristics

characterized with CDCLVD110 performance EVM, V_DD = 3.3 V, outputs not under test are terminated to 50 Ω (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_jitterLVDS	Additive phase jitter from input to LVDS output Q3 and Q3	12 kHz to 5 MHz, f_out = 30.72 MHz		281		fs rms
t_jitterLVDS	Additive phase jitter from input to LVDS output Q3 and Q3	12 kHz to 20 MHz, f_out = 125 MHz		111		fs rms

6.8 Control Register Characteristics

over recommended operating free-air temperature range, V_DD = 2.5 V ±5% (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_MAX	Maximum frequency of shift register		100	150		MHz
t_su	Set-up time, clock to SI				2	ns
t_h	Hold time, clock to SI				1.5	ns
t_removal	Removal time, enable to clock				1.5	ns
t_startup	Start-up time after disable through SI				1	µs
t_w	Clock pulse width, minimum		3			ns
V_IH	Logic input high	V_DD = 2.5 V	2			V
V_IL	Logic input low	V_DD = 2.5 V			0.8	V
I_IH	Input current, CK pin	V_I = V_DD	–5		5	µA
I_IH	Input current, SI and EN pins	V_I = V_DD	10		–30	µA
I_IL	Input current, CK pin	V_I = GND	–10		30	µA
I_IL	Input current, SI and EN pins	V_I = GND	–5		5	µA

6.9 Typical Characteristics

Input clock RMS jitter is 55.4 fs from 12 kHz to 20 MHz, additive RMS jitter is 70.4 fs, T_A = 25°C, and V_DD = 2.5 V (unless otherwise noted).

CDCLVD110A CDCLVD110A_PN_IN_OUT_CLK0_125M.gif

Figure 1. 125-MHz Input and Output Phase Noise Plot