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ZHCSMV0A August 2021 – May 2022 CDCDB803

PRODUCTION DATA

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RSL|48
- MPQF193B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RSL|48
- QFND155O

訂購信息

6.5 Electrical Characteristics

VDD, VDD_R = 3.3 V ± 5 %, ?40°C ≤ T_A ≤ 105°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{DD_R}	Core supply current	Active mode. CKPWRGD_PD# = 1				9	mA
I_{DD_R}	Core supply current	Power-down mode. CKPWRGD_PD# = 0				2.2	mA
I_DD	IO supply current	All outputs disabled				18	mA
		All outputs active, 100MHz (Per output)				7.8
		Power-down mode. CKPWRGD_PD# = 0				1.5
CLOCK INPUT
f_IN	Input frequency			50	100	250	MHz
V_IN	Input voltage swing	Differential voltage between CLKIN_P and CLKIN_N⁽¹⁾		200		2300	mV_Diff-peak
dV/dt	Input voltage edge rate	20% - 80% of input swing		0.7			V/ns
DV_CROSS	Total variation of V_CROSS	Total variation across V_CROSS			140		mV
DC_IN	Input duty cycle			40		60	%
C_IN	Input capacitance⁽²⁾	Differential capacitance between CLKIN_P and CLKIN_N pins			2.2		pF
CLOCK OUTPUT
f_OUT	Output frequency			50	100	250	MHz
C_OUT	Output capacitance⁽¹⁾	Differential capacitance between CKx_P and CKx_N pins			4		pF
V_OH	Output high voltage	Single-ended⁽²⁾ ⁽³⁾		225		270	mV
V_OL	Output low voltage	Single-ended⁽²⁾ ⁽³⁾		10		150
V_HIGH	Output high voltage	Measured into an AC load as defined in DB800ZL		660		850
V_LOW	Output low voltage	Measured into an AC load as defined in DB800ZL		–150		150
V_MAX	Output Max voltage	Measured into an AC load as defined in DB800ZL				1150
V_CROSS	Crossing point voltage	⁽³⁾ ⁽⁴⁾		130		200
V_CROSSAC	Crossing point voltage (AC load)	Measured into an AC load as defined in DB800ZL		250		550
DV_CROSS	Total variation of V_CROSS	Variation of V_CROSS ⁽³⁾ ⁽⁴⁾			35	140
V_ovs	Overshoot voltage	⁽³⁾				V_OH+75
V_ovs(AC)	Overshoot voltage (AC load)	Measured into an AC load as defined in DB800ZL				V_HIGH+300
V_uds	Undershoot voltage	⁽³⁾				V_OL–75
V_uds(AC)	Undershoot voltage	Measured into an AC load as defined in DB800ZL				V_LOW–300	mV
V_rb	Ringback Voltage	Measured into an AC load as defined in DB800ZL and taken from Single Ended waveform (relative to V_HIGHandV_LOW)		-0.2		0.2	V
Z_DIFF	Differential impedance (Default setting, 85 ?)	Measured at V_OL/V_OH		81	85	89	Ω
Z_DIFF	Differential impedance (Output impedance selection bit =1, 100 ?)	Measured at V_OL/V_OH		95	100	105
Z_{DIFF_CROSS}	Differential impedance (Default setting, 85 ?)	Measured at V_CROSS		68	85	102
Z_{DIFF_CROSS}	Differential impedance (Output impedance selection bit = 1, 100 ?)	Measured at V_CROSS		80	100	120
t_EDGE	Differential edge rate	Measured (+-150 mV) around V_CROSS ⁽⁷⁾		2		4	V/ns
Dt_EDGE	Edge rate matching	Measured (+-75 mV) V_CROSS ⁽⁷⁾				20	%
t_STABLE	Power good assertion to stable clock output	CKPWRGD_PD# pin transitions from 0 to 1, f_IN = 100 MHz	Measured when positive output reaches 0.2V			1.8	ms
t_{DRIVE_PD#}	Power good assertion to outputs driven high	CKPWRGD_PD# pin transitions from 0 to 1, f_IN = 100 MHz	Measured when positive output reaches 0.2V			300	μs
t_OE	Output enable assertion to stable clock output	OEx# pin transitions from 1 to 0				10	CLKIN Periods
t_OD	Output enable de-assertion to no clock output	OEx# pin transitions from 0 to 1				10
t_PD	Power-down assertion to no clock output	CKPWRGD_PD# pin transitions from 1 to 0				3
t_DCD	Duty cycle distortion	Differential; f_IN = 100MHz, f_{IN_DC} = 50%		–1		1	%
t_DLY	Propagation delay	⁽⁵⁾		0.5		3	ns
t_SKEW	Skew between outputs	⁽⁶⁾				50	ps
t_{DELAY(IN-OUT)}	Input to output delay variation	Input-to-output delay variation at 100 MHz across voltage and temperature		–250		250	ps
J_{CKx_DB2000Q} ⁽⁷⁾	Additive jitter for DB2000Q	DB2000Q filter, for input of 200 mV differential swing @ 1.5 V/ns				0.038	ps, RMS
J_{CKx_PCIE} ⁽⁷⁾	Additive jitter for PCIe6.0	PLL BW: 0.5 - 1 MHz; CDR = 10 MHz	Input clock slew rate = 2 V/ns			0.02	ps, RMS
	Additive jitter for PCIe5.0	PCIe5.0 filter				0.025
	Additive jitter for PCIe4.0	PLL BW = 2 - 5 MHz; CDR = 10 MHz	Input clock slew rate ≥ 1.8 V/ns			0.06
	Additive jitter for PCIe3.0	PLL BW = 2 - 5 MHz; CDR = 10 MHz	Input clock slew rate ≥ 0.6 V/ns			0.1
J_CKx	Additive jitter	f_IN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to 20 MHz integration bandwidth.			100	160	fs, RMS
NF	Noise floor	f_IN = 100 MHz; f_Offset ≥ 10 MHz	Input clock slew rate ≥ 3 V/ns		–160	-155	dBc/Hz
SMBUS INTERFACE, OEx#, CKPWRGD_PD#
V_IH	High level input voltage			2.0			V
V_IL	Low level input voltage					0.8	V
I_IH	Input leakage current	With internal pull-up/pull-down	GND ≤ V_IN ≤ V_DD	–30		30	μA
I_IL	Input leakage current	With internal pull-up/pull-down	GND ≤ V_IN ≤ V_DD	–30		30	μA
I_IH	Input leakage current	Without internal pull-up/pull-down	GND ≤ V_IN ≤ V_DD	?5		5	μA
I_IL	Input leakage current	Without internal pull-up/pull-down	GND ≤ V_IN ≤ V_DD	?5		5	μA
C_IN	Input capacitance				4.5		pF
C_OUT	Output capacitance				4.5		pF
3-LEVEL DIGITAL INTERFACE (SADR0, SADR1)
V_IH	High level input voltage			2.3			V
V_IM	Mid level input voltage			1.25	V_DD/2	1.725
V_IL	Low level input voltage					0.85
I_IH	Input leakage current	With internal pull-up/pull-down	V_IN = V_DD	–30		30	μA
I_IL	Input leakage current	With internal pull-up/pull-down	V_IN = GND	–30		30	μA
C_IN	Input capacitance⁽¹⁾				4.5		pF

(1) Voltage swing includes overshoot.

(2) Not tested in production. Ensured by design and characterization.

(3) Measured into DC test load.

(4) V_CROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is rising.

(5) Measured from rising edge of CLK_IN to any CKx output.

(6) Measured from rising edge of any CKx output to any other CKx output.

(7) Measured into AC test load.