ZHCSW43B April 2003 – October 2024 CD54ACT174 , CD74ACT174
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.