4 修訂歷史記錄
Changes from B Revision (December 2014) to C Revision
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Changed 典型應(yīng)用標(biāo)題至簡(jiǎn)化原理圖 Go
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Changed 電阻器 RVD 的位置，在簡(jiǎn)化原理圖圖形中添加了 PACK+ 和 PACK-Go
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Deleted the Lead Temperature (soldering) from the Absolute Maximum Ratings table Go
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Deleted table notes 2 through 7 from the Thermal InformationGo
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Changed resistor RVD location in Figure 9 Go
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Added title to Table 1Go
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Changed resistor RVD location, added PACK+ and PACK- in Figure 11 Go
Changes from A Revision (September 2010) to B Revision
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Added ESD 額定值表，特性 描述部分，器件功能模式，應(yīng)用和實(shí)施部分，電源相關(guān)建議部分，布局部分，器件和文檔支持部分以及機(jī)械、封裝和可訂購(gòu)信息部分Go
Changes from * Revision (June 2010) to A Revision
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Changed values in XDELAY and XDELAY_CTM electrical characteristicsGo
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Changed specifications for VOUTGo
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Changed test conditions for VOUT, IOH, and IOLGo
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Added VMM_DET_ON: VC2 = VDD = 7.6 VGo
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Changed VMM_DET_OFF: From VDD – VC2 – 7.6 V to VC2 = VDD = 7.6 VGo
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Changed content in Recommended Cell Balancing Configurations sectionGo
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Added ICD Charge Current figureGo
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Added ICD Discharge Current figureGo
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Changed XDELAY from nominally 8.0 s/µF to nominally 9.0 s/µFGo
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Changed Timing for Overvoltage Sensing figureGo
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Added Cell Imbalance Auto-Detection (Via Cell Voltage) sectionGo
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Changed VDD value in Customer Test Mode from 8.5 V to 9.5 VGo
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Changed the Voltage Test Limits figureGo
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Added External Cell Balancing sectionGo