ZHCSDI4D March 2015 – October 2022 BQ25890 , BQ25892
PRODUCTION DATA
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Revision History
- 5 說明（續(xù)）
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Functional Block Diagram
- 9.2
Feature Description
- 9.2.1 Device Power-On-Reset (POR)
- 9.2.2 Device Power Up from Battery without Input Source
- 9.2.3 Device Power Up from Input Source
- 9.2.4 Input Current Optimizer (ICO)
- 9.2.5 Boost Mode Operation from Battery
- 9.2.6 Power Path Management
- 9.2.7 Battery Charging Management
- 9.2.8 Battery Monitor
- 9.2.9 Status Outputs ( PG, STAT, and INT)
- 9.2.10 BATET (Q4) Control
- 9.2.11 Current Pulse Control Protocol
- 9.2.12 Input Current Limit on ILIM
- 9.2.13 Thermal Regulation and Thermal Shutdown
- 9.2.14 Voltage and Current Monitoring in Buck and Boost Mode
- 9.2.15 Battery Protection
- 9.2.16 Serial Interface
- 9.3 Device Functional Modes
- 9.4 Register Maps
- 10Application and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13Device and Documentation Support
- 14Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTW|24
訂購信息
7 Pin Configuration and Functions
Figure 7-1 RTW Package24-Pin WQFNTop View
Figure 7-2 RTW Package24-Pin WQFNTop View| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | BQ25890 | BQ25892 | ||
| VBUS | 1 | 1 | P | Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-μF ceramic capacitor from VBUS to PGND and place it as close as possible to IC. |
| D+ | 2 | – | AIO | Positive line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and Adjustable high voltage adapter. |
| PSEL | – | 2 | DI | Power source selection input. High indicates a USB host source and Low indicates an adapter source. |
| D– | 3 | – | AIO | Negative line of the USB data line pair.
D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and Adjustable high voltage adapter. |
| PG | – | 3 | DO | Open drain active low power good
indicator. Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if the input voltage is within VVBUS_OP, above SLEEP mode threshold (VSLEEPZ), and current limit is above IBATSRC(30 mA). |
| STAT | 4 | 4 | DO | Open drain charge status output to
indicate various charger operation. Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz. The STAT pin function can be disabled when STAT_DIS bit is set. |
| SCL | 5 | 5 | DI | I2C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor. |
| SDA | 6 | 6 | DIO | I2C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor. |
| INT | 7 | 7 | DO | Open-drain Interrupt Output. Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-μs pulse to host to report charger device status and fault. |
| OTG | 8 | 8 | DI | Active high enable pin during boost
mode. The boost mode is activated when OTG_CONFIG =1 and OTG pin is high |
| CE | 9 | 9 | DI | Active low Charge Enable pin. Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low. |
| ILIM | 10 | 10 | AI | Input current limit Input. ILIM pin sets
the maximum input current and can be used to monitor input current
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = KILIM/RILIM. The actual input current limit is the lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500 mA is not support on ILIM pin. ILIM pin can also be used to monitor input current when the voltage is below 0.8 V. The input current is proportional to the voltage on ILIM pin and can be calculated by IIN = (KILIM x VILIM) / (RILIM x 0.8) The ILIM pin function can be disabled when EN_ILIM bit is 0. |
| TS | 11 | 11 | AI | Temperature qualification voltage input.
Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor. |
| QON | 12 | 12 | DI | BATFET enable/reset control input. When BATFET is in ship mode, a logic low of tSHIPMODE (typical 1sec) duration turns on BATFET to exit shipping mode. . When VBUS is not plugged-in, a logic low of tQON_RST (typical 15sec) duration resets SYS (system power) by turning BATFET off for tBATFET_RST (typical 0.3sec) and then re-enable BATFET to provide full system power reset. The pin contains an internal pull-up to maintain default high logic |
| BAT | 13,14 | 13, 14 | P | Battery connection point to the positive
terminal of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10 μF closely to the BAT pin. |
| SYS | 15,16 | 15,16 | P | System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20 μF closely to the SYS pin. |
| PGND | 17,18 | 17,18 | P | Power ground connection for high-current
power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin. |
| SW | 19,20 | 19,20 | P | Switching node connecting to output
inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047μF bootstrap capacitor from SW to BTST. |
| BTST | 21 | 21 | P | PWM high side driver positive supply.
Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047 μF bootstrap capacitor from SW to BTST. |
| REGN | 22 | 22 | P | PWM low side driver positive supply
output. Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7 μF (10 V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin. |
| PMID | 23 | 23 | DO | Connected to the drain of the reverse
blocking MOSFET (RBFET) and the drain of HSFET. Given the total input capacitance, put 1 μF on VBUS to PGND, and the rest capacitance on PMID to PGND. |
| DSEL | 24 | – | DO | Open-drain D+/D- multiplexer selection
output. Connect the DSEL to a logic rail via 10-K? resistor. The pin is normally float and pull-up by external resistor. During Section 9.2.3.3, the pin drives low to indicate the BQ25890 D+/D- detection is in progress and needs to take control of D+, D- signals. When detection is completed, the pin keeps low when MaxCharge? adapter is detected. The pin returns to float and pulls high by external resistor when other input source type is detected. |
| NC | – | 24 | No Connect | |
| PowerPAD? | P | Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter. | ||
(1) DI (Digital Input), DO (Digital Output), DIO (Digital
Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog
Input/Output)