SLUS894B January 2010 – July 2015
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Battery Voltage Regulation
- 8.3.2 Battery Current Regulation
- 8.3.3 Precharge
- 8.3.4 Input Adapter Current Regulation
- 8.3.5 Charge Termination, Recharge, and Safety Timer
- 8.3.6 Power Up
- 8.3.7 Enable and Disable Charging
- 8.3.8 System Power Selector
- 8.3.9 Automatic Internal Soft-Start Charger Current
- 8.3.10 Converter Operation
- 8.3.11 Synchronous and Non-Synchronous Operation
- 8.3.12 Cycle-By-Cycle Charge Undercurrent Protection
- 8.3.13 Input Overvoltage Protection (ACOV)
- 8.3.14 Input Undervoltage Lockout (UVLO)
- 8.3.15 Battery Overvoltage Protection
- 8.3.16 Cycle-By-Cycle Charge Overcurrent Protection
- 8.3.17 Thermal Shutdown Protection
- 8.3.18 Temperature Qualification
- 8.3.19 Timer Fault Recovery
- 8.3.20 PG Output
- 8.3.21 CE (Charge Enable)
- 8.3.22 Charge Status Outputs
- 8.3.23 Battery Detection
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
訂購(gòu)信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2)(3)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage range | VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG | –0.3 | 33 | V |
| PH | –2 | 36 | V | |
| VFB | –0.3 | 16 | V | |
| REGN, LODRV, ACSET, TS, TTC | –0.3 | 7 | V | |
| BTST, HIDRV with respect to GND | –0.3 | 39 | V | |
| VREF, ISET1, ISET2 | –0.3 | 3.6 | V | |
| Maximum difference voltage | ACP–ACN, SRP–SRN | –0.5 | 0.5 | V |
| Junction temperature range, TJ | –40 | 155 | °C | |
| Storage temperature range, Tstg | –55 | 155 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.
(3) Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16 V. Usually, the resistor divider top resistor takes care of this.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||||
|---|---|---|---|---|---|---|---|
| Voltage range | VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG | –0.3 | 28 | V | |||
| PH | –2 | 30 | V | ||||
| VFB | –0.3 | 14 | V | ||||
| REGN, LODRV, ACSET, TS, TTC | –0.3 | 6.5 | V | ||||
| BTST, HIDRV with respect to GND | –0.3 | 34 | V | ||||
| ISET1, ISET2 | –0.3 | 3.3 | V | ||||
| VREF | 3.3 | V | |||||
| Maximum difference voltage | ACP–ACN, SRP–SRN | –0.2 | 0.2 | V | |||
| TJ | Junction temperature range | 0 | 125 | °C | |||
7.4 Thermal Information
| THERMAL METRIC(1) | bq24630 | UNIT | |
|---|---|---|---|
| RGE (VQFN) | |||
| 24 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 43 | °C/W |
| RθJCt(op) | Junction-to-case (top) thermal resistance | 54.3 | °C/W |
| RθJB | Junction-to-board thermal resistance | 20 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.6 | °C/W |
| ψJB | Junction-to-board characterization parameter | 19 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND unless otherwise noted| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| OPERATING CONDITIONS | ||||||
| VVCC_OP | VCC input voltage operating range | 5 | 28 | V | ||
| QUIESCENT CURRENTS | ||||||
| IBAT | Total battery discharge current (sum of currents into VCC, BTST, PH, ACP, ACN, SRP, SRN, VFB), VFB ≤ 2.1 V | VVCC < VSRN, VVCC > VUVLO (SLEEP) | 15 | μA | ||
| Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1 V | VVCC > VSRN, VVCC > VUVLO CE = LOW | 5 | ||||
| VVCC > VSRN, VVCC > VVCCLOW CE = HIGH, charge done | 5 | µA | ||||
| IAC | Adapter supply current (current into VCC,ACP,ACN pin) | VVCC > VSRN, VVCC > VUVLO CE = LOW | 1 | 1.5 | mA | |
| VVCC > VSRN, VVCC > VVCCLOW, CE = HIGH, charge done | 2 | 5 | ||||
| VVCC > VSRN, VVCC > VVCCLOW, CE = HIGH, charging, Qg_total = 20 nC, VVCC= 20 V | 12 | |||||
| VFB | Feedback regulation voltage | 1.8 | V | |||
| Charge voltage regulation accuracy | TJ = 0°C to 125°C | –0.5% | 0.5% | |||
| TJ = –40°C to 125°C | –0.7% | 0.7% | ||||
| Input leakage current into VFB pin | VFB = 1.8 V | 100 | nA | |||
| CURRENT REGULATION – FAST CHARGE | ||||||
| VISET1 | ISET1 voltage range | 2 | V | |||
| VIREG_CHG | SRP–SRN current sense voltage range | VIREG_CHG = VSRP – VSRN | 100 | mV | ||
| K(ISET1) | Charger current set factor amps of charge current per volt on ISET1 pin) | RSENSE = 10 mΩ | 5 | A/V | ||
| Charge current regulation accuracy | VIREG_CHG = 40 mV | –3% | 3% | |||
| VIREG_CHG = 20 mV | –4% | 4% | ||||
| VIREG_CHG = 5 mV | –25% | 25% | ||||
| VIREG_CHG = 1.5 mV (VSRN > 3.1 V) | –40% | 40% | ||||
| IISET1 | Leakage current in to ISET1 Pin | VISET1 = 2 V | 100 | nA | ||
| CURRENT REGULATION – PRECHARGE | ||||||
| Precharge current | RSENSE = 10 mΩ, VFB < VLOWV | 50 | 125 | 200 | mA | |
| CHARGE TERMINATION | ||||||
| VISET2 | ISET2 voltage range | 2 | V | |||
| Termination current range | RSENSE = 10 mΩ | 2 | A | |||
| KTERM | Termination current set factor (amps of termination current per volt on ISET2 pin) | 1 | A/V | |||
| Termination current accuracy | VITERM = 20 mV | –4% | 4% | |||
| VITERM = 5 mV | –25% | 25% | ||||
| VITERM = <1.5 mV | –45% | 45% | ||||
| Deglitch time for termination (both edge) | 100 | ms | ||||
| tQUAL | Termination qualification time | VBAT > VRECH and ICHARGE < ITERM | 250 | ms | ||
| IQUAL | Termination qualification time | Discharge current once termination is detected | 2 | mA | ||
| IISET2 | Leakage current into ISET2 pin | VISET2 = 2 V | 100 | nA | ||
| INPUT CURRENT REGULATION | ||||||
| VACSET | ACSET voltage range | 0 | 2 | V | ||
| VIREG_DPM | ACP-ACN current sense voltage range | VIREG_DPM = VACP – VACN | 0 | 100 | mV | |
| K(ACSET) | Input current set factor (amps of input current per volt on ACSET pin) | RSENSE = 10 mΩ | 5 | A/V | ||
| Input current regulation accuracy | VIREG_DPM = 40 mV | –3% | 3% | |||
| VIREG_DPM = 20 mV | –4% | 4% | ||||
| VIREG_DPM = 5 mV | –25% | 25% | ||||
| IACSET | Leakage current into ACSET pin | VACSET = 2 V | 100 | nA | ||
| INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO) | ||||||
| VUVLO | AC undervoltage rising threshold | Measure on VCC | 3.65 | 3.85 | 4 | V |
| VUVLO_HYS | AC undervoltage hysteresis, falling | 350 | mV | |||
| VCC LOWV COMPARATOR | ||||||
| Falling threshold, disable charge | Measure on VCC | 4.1 | V | |||
| Rising threshold, resume charge | 4.35 | 4.5 | V | |||
| SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) | ||||||
| VSLEEP _FALL | SLEEP falling threshold | VVCC – VSRN to enter SLEEP | 40 | 100 | 150 | mV |
| VSLEEP_HYS | SLEEP hysteresis | 500 | mV | |||
| SLEEP rising delay | VCC falling below SRN, delay to turn off ACFET | 1 | μs | |||
| SLEEP falling delay | VCC rising above SRN, delay to turn on ACFET | 30 | μs | |||
| SLEEP rising shutdown deglitch | VCC falling below SRN, delay to enter SLEEP mode | 100 | ms | |||
| SLEEP falling powerup deglitch | VCC rising above SRN, delay to exit out of SLEEP mode | 30 | ms | |||
| ACN / SRN COMPARATOR | ||||||
| VACN-SRN_FALL | ACN to SRN falling threshold | VACN – VSRN to turn on BATFET | 100 | 200 | 310 | mV |
| VACN-SRN_HYS | ACN to SRN rising hysteresis | 100 | mV | |||
| ACN to SRN rising deglitch | VACN – VSRN > VACN-SRN_RISE | 2 | ms | |||
| ACN to SRN falling deglitch | VACN – VSRN < VACN-SRN_FALL | 50 | μs | |||
| BAT LOWV COMPARATOR | ||||||
| VLOWV | Precharge to fastcharge transition (LOWV threshold) | Measured on VFB pin, rising | 0.333 | 0.35 | 0.367 | V |
| VLOWV_HYS | LOWV hysteresis | 100 | mV | |||
| LOWV rising deglitch | VFB falling below VLOWV | 25 | ms | |||
| LOWV falling deglitch | VFB rising above VLOWV | 25 | ms | |||
| RECHARGE COMPARATOR | ||||||
| VRECHG | Recharge threshold (with respect to VREG) | Measured on VFB pin, rising | 110 | 125 | 140 | mV |
| Recharge rising deglitch | VFB decreasing below VRECHG | 10 | ms | |||
| Recharge falling deglitch | VFB increasing above VRECHG | 10 | ms | |||
| BAT OVERVOLTAGE COMPARATOR | ||||||
| VOV_RISE | Overvoltage rising threshold | As percentage of VFB | 108% | |||
| VOV_FALL | Overvoltage falling threshold | As percentage of VFB | 105% | |||
| INPUT OVERVOLTAGE COMPARATOR (ACOV) | ||||||
| VACOV | AC overvoltage, rising threshold on VCC | 31.04 | 32 | 32.96 | V | |
| VACOV_HYS | AC overvoltage, falling hysteresis | 1 | V | |||
| AC overvoltage, deglitch (both edges) | Delay to changing the STAT pins | 1 | ms | |||
| AC overvoltage, rising deglitch | Delay to disable charge | 1 | ms | |||
| AC overvoltage, falling deglitch | Delay to resume charge | 20 | ms | |||
| THERMAL SHUTDOWN COMPARATOR | ||||||
| TSHUT | Thermal shutdown, rising temperature | Temperature increasing | 145 | °C | ||
| TSHUT_HYS | Thermal shutdown hysteresis | 15 | °C | |||
| Thermal shutdown rising deglitch | Temperature increasing | 100 | μs | |||
| Thermal shutdown falling deglitch | Temperature decreasing | 10 | ms | |||
| THERMISTOR COMPARATOR | ||||||
| VLTF | Cold temperature, rising threshold | Charger suspended below this temperature | 72.5% | 73.5% | 74.5% | |
| VLTF_HYS | Cold temperature hysteresis | 0.2% | 0.4% | 0.6% | ||
| VCOOL | Cool temperature rising threshold | Charger enabled, cuts back to ICHARGE/8 below this temperature | 70.2% | 70.7% | 71.2% | |
| VCOOL_HYS | Cool temperature hysteresis | 0.2% | 0.6% | 1.0% | ||
| VWARM | Warm temperature rising threshold | Charger cuts back to ICHARGE/8 above this temperature | 47.5% | 48% | 48.5% | |
| VWARM_HYS | Warm temperature hysteresis | 1.0% | 1.2% | 1.4% | ||
| VHTF | Hot temperature rising threshold | Charger suspended above this temperature before initiating charge | 36.2% | 37% | 37.8% | |
| VTCO | Cutoff temperature rising threshold | Charger suspended above this temperature during initiating charge | 33.7% | 34.4% | 35.1% | |
| Deglitch time for temperature out-of-range detection | VTS > VLTF, or VTS < VTCO, or VTS < VHTF | 400 | ms | |||
| Deglitch time for temperature in-valid-range detection | VTS < VLTF – VLTF_HYS or VTS >VTCO or VTS > VHTF | 20 | ms | |||
| Deglitch time for current reduction to ICHARGE/8 due to warm or cool temperature | VTS > VCOOL, or VTS < VWARM | 25 | ms | |||
| Deglitch time to charge at ICHARGE from ICHARGE/8 when resuming from warm or cool temperatures | VTS < VCOOL – VCOOL_HYS, or VTS > VWARM – VWARM_HYS | 25 | ms | |||
| Charge current due to warm or cool temperatures | VCOOL < VTS < VLTF, or VWARM < VTS < VHTF, or VWARM < VTS < VTCO | ICHARGE/8 | ||||
| CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
| VOC | Charge overcurrent falling threshold | Current rising, in non-synchronous mode, mesure on V(SRP-SRN), VSRP < 2 V | 45.5 | mV | ||
| Current rising, as percentage of V(IREG_CHG), in synchronous mode, VSRP > 2.2 V | 160% | |||||
| Charge overcurrent threshold floor | Minimum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2 V | 50 | mV | |||
| Charge overcurrent threshold ceiling | Maximum OCP threshold in synchronous mode, measure on V(SRP-SRN), VSRP > 2.2 V | 180 | mV | |||
| CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
| VISYNSET | Charge under-current falling threshold | Switch from SYNCH to NON-SYNCH, VSRP > 2.2 V | 1 | 5 | 9 | mV |
| BATTERY SHORTED COMPARATOR (BATSHORT) | ||||||
| VBATSHT | BAT short falling threshold, forced non-synchronous mode | VSRP falling | 2 | V | ||
| VBATSHT_HYS | BAT short rising hysteresis | 200 | mV | |||
| VBATSHT_DEG | Deglitch on both edge | 1 | μs | |||
| LOW CHARGE CURRENT COMPARATOR | ||||||
| VLC | Average low charge current falling threshold | Measure on V(SRP-SRN), forced into non-synchronous mode | 1.25 | mV | ||
| VLC_HYS | Low charge current rising hysteresis | 1.25 | mV | |||
| VLC_DEG | Deglitch on both edge | 1 | μs | |||
| VREF REGULATOR | ||||||
| VVREF_REG | VREF regulator voltage | VVCC > VUVLO, (0 – 35 mA load) | 3.267 | 3.3 | 3.333 | V |
| IVREF_LIM | VREF current limit | VVREF = 0 V, VVCC > VUVLO | 35 | mA | ||
| REGN REGULATOR | ||||||
| VREGN_REG | REGN regulator voltage | VVCC > 10 V, CE = HIGH (0–40 mA load) | 5.7 | 6 | 6.3 | V |
| IREGN_LIM | REGN current limit | VREGN = 0 V, VVCC > VUVLO | 40 | mA | ||
| TTC INPUT | ||||||
| TPRECHG | Precharge safety timer range(1) | Precharge time before fault occurs | 1440 | 1800 | 2160 | s |
| TCHARGE | Fast-charge saftey timer range, with ±10% accuracy(1) | Tchg = CTTC × KTTC | 1 | 10 | h | |
| Fast charge timer accuracy(1) | 0.047 μF ≤ CTTC ≤ 0.47 μF | –10% | 10% | |||
| KTTC | Timer multiplier | 1.4 | min/nF | |||
| TTC low threshold | VTTC below this threshold disables the safety timer and termination | 0.4 | V | |||
| TTC comparator high threshold | 1.5 | V | ||||
| TTC comparator low threshold | 1 | V | ||||
| TTC source/sink current | 45 | 50 | 55 | μA | ||
| BATTERY SWITCH (BATFET) DRIVER | ||||||
| RDS_BAT_OFF | BATFET turnoff resistance | VACN > 5 V | 150 | Ω | ||
| RDS_BAT_ON | BATFET turnon resistance | VACN > 5 V | 20 | kΩ | ||
| VBATDRV_REG | BATFET drive voltage | VBATDRV_REG = VACN – VBATDRV when VACN > 5 V and BATFET is on | 4.2 | 7 | V | |
| AC SWITCH (ACFET) DRIVER | ||||||
| RDS_AC_OFF | ACFET turnoff resistance | VVCC > 5 V | 30 | ? | ||
| RDS_AC_ON | ACFET turnon resistance | VVCC > 5 V | 20 | k? | ||
| VACDRV_REG | ACFET drive voltage | VACDRV_REG = VVCC – VACDRV when VVCC > 5 V and ACFET is on | 4.2 | 7 | V | |
| AC / BAT MOSFET DRIVERS TIMING | ||||||
| Driver dead time | Dead time when switching between AC and BAT | 10 | μs | |||
| BATTERY DETECTION | ||||||
| tWAKE | Wake timer | Max. time charge is enabled | 500 | ms | ||
| IWAKE | Wake current | RSENSE = 10 mΩ | 50 | 125 | 200 | mA |
| tDISCHARGE | Discharge timer | Max time discharge current is applied | 1 | sec | ||
| IDISCHARGE | Discharge current | 8 | mA | |||
| IFAULT | Fault current after a timeout fault | 2 | mA | |||
| VWAKE | Wake threshold (with respect to VREG) | Voltage on VFB to detect battery absent during wake | 125 | mV | ||
| VDISCH | Discharge threshold | Voltage on VFB to detect battery absent during discharge | 0.35 | V | ||
| PWM HIGH SIDE DRIVER (HIDRV) | ||||||
| RDS_HI_ON | High Side driver (HSD) turnon resistance | VBTST – VPH = 5.5 V | 3.3 | 6 | Ω | |
| RDS_HI_OFF | High Side driver turnoff resistance | VBTST – VPH = 5.5 V | 1 | 1.3 | Ω | |
| VBTST_REFRESH | Bootstrap refresh comparator threshold voltage | VBTST – VPH when low side refresh pulse is requested | 4 | 4.2 | V | |
| PWM LOW SIDE DRIVER (LODRV) | ||||||
| RDS_LO_ON | Low side driver (LSD) turnon resistance | 4.1 | 7 | Ω | ||
| RDS_LO_OFF | Low side driver turnoff resistance | 1 | 1.4 | Ω | ||
| PWM DRIVERS TIMING | ||||||
| Driver dead time | Dead time when switching between LSD and HSD, no load at LSD and HSD | 30 | ns | |||
| PWM OSCILLATOR | ||||||
| VRAMP_HEIGHT | PWM ramp height | As percentage of VCC | 7% | |||
| PWM switching frequency(1) | 255 | 300 | 345 | kHz | ||
| INTERNAL SOFT START (8 Steps to Regulation Current ICHG) | ||||||
| Soft-start steps | 8 | step | ||||
| Soft-start step time | 1.6 | ms | ||||
| CHARGER SECTION POWER-UP SEQUENCING | ||||||
| Charge-enable delay after power up | Delay from when adapter is detected to when the charger is allowed to turn on | 1.5 | s | |||
| LOGIC IO PIN CHARACTERISTICS | ||||||
| VIN_LO | CE input low threshold voltage | 0.8 | V | |||
| VIN_HI | CE input high threshold voltage | 2.1 | V | |||
| VBIAS_CE | CE input bias current | V = 3.3 V (CE has internal 1-MΩ pulldown resistor) | 6 | μA | ||
| VOUT_LO | STAT1, STAT2, PG output low saturation voltage | Sink current = 5 mA | 0.5 | V | ||
| IOUT_HI | Leakage current | V = 32 V | 1.2 | µA | ||
(1) Verified by design.
7.6 Typical Characteristics
Table 1. Table of Graphs
| FIGURE | ||
|---|---|---|
| REF, REGN, and PG Power Up (CE = 1) | Figure 1 | |
| Charge Enable | Figure 2 | |
| Current Soft-Start (CE,=,1) | Figure 3 | |
| Charge Disable | Figure 4 | |
| Continuous-Conduction-Mode Switching Waveforms | Figure 5 | |
| Cycle-by-Cycle Synchronous to Nonsynchronous | Figure 6 | |
| 100% Duty and Refresh Pulse | Figure 7 | |
| Transient System Load (DPM) | Figure 8 | |
| Battery Insertion | Figure 9 | |
| Battery-to-Ground Short Protection | Figure 10 | |
| Battery-to-Ground Short Transition | Figure 11 | |
| Efficiency vs Output Current | Figure 12 | |
| Input ACOV Transition | Figure 13 | |
| Input ACOV Resume Normal Transition | Figure 14 | |
Figure 1. REF, REGN, and PG Power Up (CE = 1)
Figure 3. Current Soft-Start (CE = 1)
Figure 5. Continuous-Conduction Mode Switching Waveform
Figure 7. 100% Duty and Refresh Pulse
Figure 9. Battery Insertion
Figure 11. Battery-to-GND Short Transition
Figure 13. Input ACOV Transition
Figure 2. Charge Enable
Figure 4. Charge Disable
Figure 6. Cycle-by-Cycle Synchronous to Nonsynchronous
Figure 8. Transient System Load (DPM)
Figure 10. Battery-to-GND Short Protection
Figure 12. Efficiency vs Output Current
Figure 14. Input ACOV Resume Normal Transition