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ZHCSBL4A September 2013 – January 2015

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- MPQF124G

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- QFND136Y

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Voltage (with respect to GND)	VBUS (converter not switching)	–2	15⁽²⁾	V
	PMID (converter not switching)	–0.3	15⁽²⁾	V
	STAT	–0.3	12	V
	BTST	–0.3	12	V
	SW	–2	7 8 (Peak for 20ns duration)	V
	BAT, SYS (converter not switching)	–0.3	6	V
	SDA, SCL, INT, OTG, ILIM, REGN, TS, QON, CE, D+, D–,	–0.3	7	V
	BTST TO SW	–0.3	7	V
	PGND to GND	–0.3	0.3	V
Output sink current	INT, STAT		6	mA
Junction temperature		–40	150	°C
Storage temperature range, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground pin unless otherwise noted.

(2) VBUS is specified up to 16 V for a maximum of 24 hours under no load conditions.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

		MIN	MAX	UNIT
V_IN	Input voltage	3.9	6.2⁽¹⁾	V
I_IN	Input current (VBUS)		3	A
I_SYS	Output current (SYS)		3.5	A
V_BAT	Battery voltage		4.4	V
I_BAT	Fast charging current		3	A
I_BAT	Discharging current with internal MOSFET		5.5	A
T_A	Operating free-air temperature range	–40	85	°C

(1) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq24295	UNIT
THERMAL METRIC⁽¹⁾		RGE (24 PIN)	UNIT
R_θJA	Junction-to-ambient thermal resistance	32.2	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	29.8
R_θJB	Junction-to-board thermal resistance	9.1
ψ_JT	Junction-to-top characterization parameter	0.3
ψ_JB	Junction-to-board characterization parameter	9.1
R_θJCbot	Junction-to-case (bottom) thermal resistance	2.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_{VBUS_UVLOZ} < V_VBUS < V_ACOV and V_VBUS > V_BAT + V_SLEEP, T_J = –40°C to 125°C and T_J = 25°C for typical values unless other noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
QUIESCENT CURRENTS
I_BAT	Battery discharge current (BAT, SW, SYS)	V_VBUS < V_UVLO, VBAT = 4.2 V, leakage between BAT and VBUS		5		µA
		High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), –40°C – 85°C		16	20	µA
		High-Z Mode, or no VBUS, BATFET enabled (REG07[5] = 0), –40°C – 85°C		32	55	µA
I_VBUS	Input supply current (VBUS)	V_VBUS = 5 V, High-Z mode, No battery		15	30	µA
		V_VBUS > V_UVLO, V_VBUS > V_BAT, converter not switching		1.5	3	mA
		V_VBUS > V_UVLO, V_VBUS > V_BAT, converter switching, V_BAT = 3.2 V, I_SYS = 0 A		4		mA
		V_VBUS > V_UVLO, V_VBUS > V_BAT, converter switching, charge disable, V_BAT = 3.8 V, I_SYS = 100 µA		3.5		mA
I_BOOST	Battery discharge current in boost mode	VBAT = 4.2 V, Boost mode, I_PMID = 0 A, converter switching		3.5		mA
VBUS/BAT POWER UP
V_{VBUS_OP}	VBUS operating voltage		3.9		6.2	V
V_{VBUS_UVLOZ}	VBUS for active I²C, no battery	V_VBUS rising	3.6			V
V_SLEEP	Sleep mode falling threshold	V_VBUS falling, V_VBUS-VBAT	35	80	120	mV
V_SLEEPZ	Sleep mode rising threshold	V_VBUS rising, V_VBUS-VBAT	170	250	350	mV
V_ACOV	VBUS over-voltage rising threshold	V_VBUS rising	6.2		6.6	V
V_{ACOV_HYST}	VBUS over-voltage falling hysteresis	V_VBUS falling		250		mV
V_{BAT_UVLOZ}	Battery for active I²C, no VBUS	V_BAT rising	2.3			V
V_{BAT_DPL}	Battery depletion threshold	V_BAT falling		2.4	2.6	V
V_{BAT_DPL_HY}	Battery depletion rising hysteresis	V_BAT rising		200		mV
V_VBUSMIN	Bad adapter detection threshold	V_VBUS falling		3.8		V
I_BADSRC	Bad adapter detection current source			30		mA
POWER PATH MANAGEMENT
V_{SYS_MAX}	Typical system regulation voltage	Isys = 0 A, BATFET (Q4) off, V_BATup to 4.2 V, REG01[3:1] = 101, V_SYSMIN = 3.5 V	3.5		4.35	V
V_{SYS_MIN}	System voltage outpu	REG01[3:1] = 101, V_SYSMIN = 3.5 V	3.5	3.65		V
R_ON(RBFET)	Top reverse blocking MOSFET on-resistance between VBUS and PMIID			28	41	mΩ
R_ON(HSFET)	Internal top switching MOSFET on-resistance between PMID and SW	T_J = –40°C – 85°C		39	51	mΩ
R_ON(HSFET)		T_J = -40°C – 125°C		39	58	mΩ
R_ON(LSFET)	Internal bottom switching MOSFET on-resistance between SW and PGND	T_J = –40°C – 85°C		61	82	mΩ
R_ON(LSFET)		T_J = -40°C – 125°C		61	90	mΩ
V_FWD	BATFET forward voltage in supplement mode	BAT discharge current 10mA		30		mV
V_{SYS_BAT}	SYS/BAT comparator	V_SYS falling		70		mV
V_BATGD	Battery good comparator rising threshold	V_BAT rising		3.55		V
V_{BATGD_HYST}	Battery good comparator falling threshold	V_BAT falling		100		mV
BATTERY CHARGER
V_{BAT_REG_ACC}	Charge voltage regulation accuracy	V_BAT = 4.112 V and 4.208 V	–0.5%		0.5%
I_{ICHG_REG_ACC}	Fast charge current regulation accuracy	V_BAT = 3.8 V, I_CHG = 1024 mA, T_J = 25°C	-4%		4%
		V_BAT = 3.8 V, I_CHG = 1024 mA, T_J = -20°C – 125°C	-7%		7%
		V_BAT = 3.8 V, I_CHG = 1792 mA, T_J = -20°C – 125°C	–10%		10%
I_{CHG_20pct}	Charge current with 20% option on	V_BAT = 3.1 V, I_CHG = 104 mA, REG02 = 03 and REG02[0] = 1	75		175	mA
V_BATLOWV	Battery LOWV falling threshold	Fast charge to precharge, REG04[1] = 1	2.6	2.8	2.9	V
V_{BATLOWV_HYST}	Battery LOWV rising threshold	Precharge to fast charge, REG04[1] = 1 (Typical 200-mV hysteresis)	2.8	3.0	3.1	V
I_{PRECHG_ACC}	Precharge current regulation accuracy	VBAT = 2.6 V, I_CHG = 256 mA	–20%		20%
I_{TYP_TERM_ACC}	Typical termination current	I_TERM = 256 mA, I_CHG = 2048 mA		265		mA
I_{TERM_ACC}	Termination current accuracy	I_TERM = 256 mA, I_CHG = 2048 mA	–22.5%		22.5%
V_SHORT	Battery short voltage	VBAT falling		2.0		V
V_{SHORT_HYST}	Battery Short Voltage hysteresis	VBAT rising		200		mV
I_SHORT	Battery short current	VBAT < 2.2 V		100		mA
V_RECHG	Recharge threshold below VBAT_REG	VBAT falling, REG04[0] = 0		100		mV
t_RECHG	Recharge deglitch time	VBAT falling, REG04[0] = 0		20		ms
R_{ON_BATFET}	SYS-BAT MOSFET on-resistance	T_J = 25°C		24	28	mΩ
R_{ON_BATFET}	SYS-BAT MOSFET on-resistance	T_J = –40°C – 125°C		24	35	mΩ
INPUT VOLTAGE/CURRENT REGULATION
V_{INDPM_REG_ACC}	Input voltage regulation accuracy		-2%		2%
I_{USB_DPM}	USB Input current regulation limit, VBUS = 5V, current pulled from SW	USB100	85		100	mA
		USB150	125		150	mA
		USB500	440		500	mA
		USB900	750		900	mA
I_{ADPT_DPM}	Input current regulation accuracy	IADP = 1.5 A, REG00[2:0] = 101	1.3		1.5	A
I_{IN_START}	Input current limit during system start up	VSYS < 2.2 V		100		mA
K_ILIM	I_IN = K_ILIM/R_ILIM	IINDPM = 1.5 A	395	435	475	A x Ω
D+/D- DETECTION
V_{D+_SRC}	D+ voltage source		0.5		0.7	V
I_{D+_SRC}	D+ connection check current source		7		14	µA
I_{D–_SINK}	D– current sink		50	100	150	µA
I_{D_LKG}	Leakage current into D+/D–	D–, switch open	–1		1	µA
I_{D_LKG}	Leakage current into D+/D–	D+, switch open	–1		1	µA
V_{D+_LOW}	D+ low comparator threshold				0.8	V
V_{D–_LOWdatref}	D– low comparator threshold		250		400	mV
R_{D–_DWN}	D– pulldown for connection check		14.25		24.8	kΩ
t_{SDP_DEFAULT}	Charging timer with 100mA USB host in default mode				45	mins
V_{adpt1_lo}	D+ low comparator threshold for non-standard adapter Divider-1	As percentage of REGN, 0°C – 85°C⁽¹⁾	46.5%	48%	49.5%
V_{adpt1_hi}	D+ low comparator threshold for non-standard adapter divider-1	As percentage of REGN, 0°C – 85°C⁽¹⁾	58.5%	60%	61.5%
V_{adpt2_lo}	D+ low comparator threshold for non-standard adapter divider-2	As percentage of REGN, 0°C – 85°C⁽¹⁾	15.5%	17%	18.5%
V_{adpt2_hi}	D+ low comparator threshold for Non-standard adapter divider-2	As percentage of REGN, 0°C – 85°C⁽¹⁾	28.5%	30%	31.5%
V_{adpt3_lo}	D- low comparator threshold for non-standard adapter divider-3	As percentage of REGN, 0°C – 85°C⁽¹⁾	46.5%	48%	49.5%
V_{adpt3_hi}	D- high comparator threshold for non-standard adapter divider-3	As percentage of REGN, 0°C – 85°C⁽¹⁾	58.5%	60%	61.5%
BAT OVER-VOLTAGE PROTECTION
V_BATOVP	Battery over-voltage threshold	V_BAT rising, as percentage of V_{BAT_REG}		104%
V_{BATOVP_HYST}	Battery over-voltage hysteresis	V_BAT falling, as percentage of V_{BAT_REG}		2%
t_BATOVP	Battery over-voltage deglitch time to disable charge			1		µs
THERMAL REGULATION AND THERMAL SHUTDOWN
T_{Junction_REG}	Junction temperature regulation accuracy	REG06[1:0] = 11		120		°C
T_SHUT	Thermal shutdown rising temperature	Temperature increasing		160		°C
T_{SHUT_HYS}	Thermal shutdown hysteresis			30		°C
	Thermal shutdown rising deglitch	Temperature increasing delay		1		ms
	Thermal shutdown falling deglitch	Temperature decreasing delay		1		ms
COLD/HOT THERMISTER COMPARATOR
V_LTF	Cold temperature threshold, TS pin voltage rising threshold	Charger suspends charge. as percentage to V_REGN	73%	73.5%	74%
V_{LTF_HYS}	Cold temperature hysteresis, TS pin voltage falling	As percentage to V_REGN		0.4%
V_HTF	Hot temperature TS pin voltage rising threshold	As percentage to V_REGN	46.6%	47.2%	48.8%
V_TCO	Cut-off temperature TS pin voltage falling threshold	As percentage to V_REGN	44.2%	44.7%	45.2%
	Deglitch time for temperature out of range detection	V_TS > V_LTF, or V_TS < V_TCO, or V_TS < V_HTF		10		ms
VBCOLD0	Cold temperature threshold, TS pin voltage rising threshold	As percentage to V_REGN REG02[1] = 0 (Approx. -10°C w/ 103AT)	75.5%	76%	76.5%
VBCOLD0_HYS		As percentage to V_REGN REG02[1] = 0 (Approx. 1°C w/ 103AT)		1%
VBCOLD1	Cold temperature threshold 1, TS pin voltage rising threshold	As percentage to V_REGN REG02[1] = 1 (Approx. -20°C w/ 103AT)	78.5%	79%	79.5%
VBCOLD1_HYS		As percentage to V_REGN REG02[1] = 1 (Approx. 1°C w/ 103AT)		1%
VBHOT0	Hot temperature threshold, TS pin voltage falling threshold	As percentage to V_REGN REG06[3:2] = 01 (Approx. 55°C w/ 103AT)	35.5%	36%	36.5%
VBHOT0_HYS		As percentage to V_REGN REG06[3:2] = 01 (Approx. 3°C w/ 103AT)		3%
VBHOT1	Hot temperature threshold 1, TS pin voltage falling threshold	As percentage to V_REGN REG06[3:2] = 00 (Approx. 60°C w/ 103AT)	32.5%	33%	33.5%
VBHOT1_HYS		As percentage to V_REGN REG06[3:2] = 00 (Approx. 3°C w/ 103AT)		3%
VBHOT2	Hot temperature threshold 2, TS pin voltage falling threshold	As percentage to V_REGN REG06[3:2] = 10 (Approx. 65°C w/ 103AT)	29.5%	30%	30.5%
VBHOT2_HYS		As percentage to V_REGN REG06[3:2] = 10 (Approx. 3°C w/ 103AT)		3%
CHARGE OVER-CURRENT COMPARATOR
I_{HSFET_OCP}	HSFET cycle by cycle over-current threshold		5.3	7.5		A
I_{BATFET_OCP}	System over load threshold		5.5	6.6		A
V_{LSFET_UCP}	LSFET charge under-current falling threshold	From sync mode to non-sync mode		100		mA
F_SW	PWM Switching frequency, and digital clock		1300	1500	1700	kHz
D_MAX	Maximum PWM duty cycle			97%
V_{BTST_REFRESH}	Bootstrap refresh comparator threshold	VBTST-VSW when LSFET refresh pulse is requested, VBUS = 5 V		3.6		V
BOOST MODE OPERATION
V_{OTG_REG}	Boost mode output voltage	I(PMID) = 0, REG06[7:4] = 1001 (5.126 V)		5.12		V
V_{OTG_REG_ACC}	Boost mode output voltage accuracy	I(PMID) = 0, REG06[7:4] = 1001 (5.126 V)	-3%		3%
V_{OTG_BAT}	Battery voltage exiting boost mode	BAT falling, REG04[1] = 1	2.9			V
I_OTG	Boost mode output current on PMID		1.3			A
V_{OTG_OVP}	OTG over-voltage threshold	Rising threshold	5.8	6		V
V_{OTG_OVP_HYS}	OTG over-voltage threshold hysteresis	Falling threshold		300		mV
I_{OTG_LSOCP}	LSFET cycle by cycle current limit		5			A
I_{OTG_HSZCP}	HSFET under current falling threshold			100		mA
REGN LDO
V_REGN	REGN LDO output voltage	V_VBUS = 6 V, I_REGN = 40 mA	4.8	5	5.5	V
V_REGN	REGN LDO output voltage	V_VBUS = 5 V, I_REGN = 20 mA	4.7	4.8		V
I_REGN	REGN LDO current limit	V_VBUS = 5 V, V_REGN = 3.8 V	50			mA
LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON)
V_ILO	Input low threshold				0.4	V
V_IH	Input high threshold (CE, STAT, QON)		1.3			V
V_{IH_OTG}	Input high threshold (OTG)		1.1			V
V_{OUT_LO}	Output low saturation voltage	Sink current = 5 mA			0.4	V
I_BIAS	High level leakage current (OTG, CE, STAT )	Pull-up rail 1.8 V			1	µA
I_BIAS	High level leakage current (QON)	Pull-up rail 3.6 V			8	µA
I²C INTERFACE (SDA, SCL, INT)
V_IH	Input high threshold level	VPULL-UP = 1.8 V, SDA and SCL	1.3			V
V_IL	Input low threshold level	VPULL-UP = 1.8 V, SDA and SCL			0.4	V
V_OL	Output low threshold level	Sink current = 5 mA			0.4	V
I_BIAS	High-level leakage current	VPULL-UP = 1.8 V, SDA and SCL			1	µA
f_SCL	SCL clock frequency				400	kHz
DIGITAL CLOCK AND WATCHDOG TIMER
f_HIZ	Digital crude clock	REGN LDO disabled	15	35	50	kHz
f_DIG	Digital clock	REGN LDO enabled	1300	1500	1700	kHz

(1) REGN LDO is configured in drop-out mode. VBUS is close to REGN when I_REGN = 0 mA.

7.6 Timing Requirements

			MIN	TYP	UNIT
VBUS/BAT POWER UP
t_BADSRC	Bad source detection duration			30	ms
QON TIMING
t_QON	QON pin high time to turn on BATFET		2		ms
DIGITAL CLOCK AND WATCHDOG TIMER
t_WDT	REG05[5:4] = 11	REGN LDO disabled	112	160	sec
t_WDT	REG05[5:4] = 11	REGN LDO enabled	136	160	sec

Figure 1. I²C-Compatible Interface Timing Diagram

7.7 Typical Characteristics

Table 1. Table of Figures

	FIGURE
Charging Efficiency vs Charging Current (DCR = 10 mΩ)	Figure 2
System Efficiency vs System Load Current (DCR = 10 mΩ)	Figure 3
Boost Mode Efficiency vs VBUS Load Current (DCR = 10 mΩ)	Figure 4
SYS Voltage Regulation vs System Load Current	Figure 5
Boost Mode PMID Voltage Regulation (Typical Output = 5.126 V, REG06[7:4] = 1001) vs PMID Load Current	Figure 6
SYS Voltage vs Temperature	Figure 7
BAT Voltage vs Temperature	Figure 8
Input Current Limit vs Temperature	Figure 9
Charge Current vs Package Temperature	Figure 10